High Frequency Current Paths Always Follow the Path of Least Impedance - Not Resistance.
As just discussed, the lowest impedance path of a high speed signal is directly under a PCB trace. This minimizes the current loop area substantially. The “worst” case scenario shows a long winding trace creates a large current loop area which is made even worse by the break in the ground plane. The obvious issue with this is the ground plane is often used as a reference point for other parts of the system. If the current flow density is high near one of these reference points, this can (and often does) cause noise to occur in the circuit and often propagates throughout the entire signal flow.
As the bad layout shows, also shows a long winding trace that does not follow the “shortest distance between two points is a straight line” method. The better layout minimizes the distance while reducing the current loop area. But, the best way to do the layout is to place the receiver part as close as possible to the input. This easily is the smallest loop area and delays in the signal path are drastically reduced. A key benefit of this method is the reference ground point for other circuits are kept “quiet” and should have no contribution from the undesirable current flow.
This also minimizes the need for adhering to strict strip-line techniques as the signal path acts as a lumped circuit and not a distributed circuit. A lumped circuit typically has rising edges much less than the delay time of the transmission line, thus minimizing issues. The construction of transmission lines naturally keeps the source and return currents close to each other. This helps minimize current loop area and drastically reduces noise along the path on the PCB and also EMI.
This blog presents the most common design issues affecting signal integrity in high-speed digital hardware design. These include impedance control, terminations, ground/power planes, signal routing and crosstalk. Armed with the knowledge presented here, a digital designer will be able to recognize potential signal integrity problems at the earliest design stage. Also, they will be able to apply techniques presented to prevent these issues affecting the performance of their design.
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