Gigabit Ethernet Controller Design Consideration --> Ethernet Magnetic Layout Considerations

The Ethernet magnetic layout considerations are dependent on the external PHY. Please refer to the preferred external PHY Ethernet magnetic layout guide for the detailed requirements.


The following are some general Gigabit Ethernet layout considerations for the differential signals of the Gigabit Ethernet PHY, the Ethernet magnetic and the RJ-45 connector. All trace routes from 10/100/1000M magnetic, RJ-45, and Gigabit Ethernet PHY should be as short as possible. It is an appropriate policy to have the same length for all differential pair signal traces. General speaking, reducing signal crosstalk, providing a solid ground plane, and decreasing parallel route should be considered.

1. The crystal/oscillator clock source and the switching noises from digital signals should be kept away from the MDI0±, MDI1±, MDI2±, and MDI3± differential pairs. Moreover, the crystal/oscillator may be sensitive to wander capacitances and noise from other signals; it is better to deploy the crystal far away from I/O ports, high frequency signal traces, magnetic, board edges, and so on.
2. The Ethernet magnetic should be placed as close to the RJ-45 connector as possible.
3. The Gigabit Ethernet PHY should be placed as close as possible to the magnetic. If there are some limitations on the PCB layout, the trace length from the Gigabit Ethernet PHY to the magnetic should not be longer than 5 inches.
4. The MDI0±, MDI1±, MDI2±, and MDI3± differential pairs should be routed as close as possible. The trace spacing D1 between MDI0+ and MDI0- (or between MDI1+ and MDI1-, MDI2+ and MDI2-, MDI3+ and MDI3-) pair should be in 8 ~ 10 mils. The trace width should be adjusted accordingly to yield the required trace impedance.
5. The spacing D2 should be larger than 200 mils. If the PCB layout is really difficult to meet this requirement, the D2 spacing should be as larger as possible.
6. Route the MDI0±, MDI1±, MDI2±, and MDI3± differential pairs as straight as possible and keep them in parallel for differential pairs.
7. Keep the trace length difference between MDI0+ and MDI0- (or between MDI1+ and MDI1-, MDI2+ and MDI2-, MDI3+ and MDI3-) pair within 700 mils.
8. The termination resistors 49.9Ω and capacitors of the MDI0±, MDI1±, MDI2± and MDI3± differential pairs should be placed as close to the magnetic as possible and the trace should be shorter than 400 mils.
9. Route the MDI0±, MDI1±, MDI2±, and MDI3± differential pairs running symmetric, equal length and close whenever possible.
10. Avoid using vias on the traces of the MDI0±, MDI1±, MDI2±, and MDI3± differential pairs. If the PCB layout really needs to use vias on the differential pairs, please match the vias to keep the differential pairs balanced.
11. The power plane and digital ground plane should not be placed under the magnetic and RJ-45 connector.
12. Avoid routing the signal trace with right angle, instead, the signal trace should be routed with multiple 45˚ angles.