HDMI Design Guidelines -- > Layer Stack-up, Differential Pair

Introduction

This article presents design guidelines for helping users of HDMI mux-repeaters to maximise the device’s full performance through careful printed circuit board (PCB) design. We’ll explain important concepts of some main aspects of high-speed PCB design with recommendations.
This discussion will cover layer stack, differential traces, controlled impedance transmission
lines, discontinuities, routing guidelines, reference planes, vias and decoupling capacitors.

Layer stack

The pin-out of a HDMI mux-repeater is tailored for the design in HDTV receiver circuits (see Picture below). Each side of the package provides a HDMI port, featuring four differential TMDS signal pairs, thus resulting in three input and one output port. The remaining signals comprise the supply rails, Vcc and ground, and lower speed signals such as the I2C interface, Hotplug-detect and the mux-selector pins.

FIG 1. The device pin-out is tailored for HDTV receiver applications

A minimum of four layers are required to accomplish a low EMI PCB design (see Figure 2). Layer stacking should be in the following order (top-to-bottom): TMDS signal layer, ground plane, power plane and control signal layer.

FIG 2. Recommended 4- or 6- layer stack for a receiver PCB design

• Routing the high-speed TMDS traces on the top layer avoids the use of vias (and the introduction of their inductances) and allows for clean interconnects from the HDMI connectors to the repeater inputs, and from the repeater output to the subsequent receiver circuit.
• Placing a solid ground plane next to the high-speed signal layer establishes controlled impedance for transmission line interconnects and provides an excellent low-inductance path for the return current flow.
• Placing the power plane next to the ground plane creates additional high-frequency bypass capacitance.
• Routing the slower speed control signals on the bottom layer allows for greater flexibility as
• these signal links usually have margin to tolerate discontinuities such as vias.

If an additional supply voltage plane or signal layer is needed, add a second power / ground
plane system to the stack to keep it symmetrical. This makes the stack mechanically stable and prevents it from warping. Also the power and ground plane of each power system can be placed closer together, thus increasing the high-frequency bypass capacitance significantly.

Differential Traces

HDMI uses transition minimised differential signalling (TMDS) for transmitting high-speed serial data. Differential signalling offers significant benefits over single ended signalling.

In single-ended systems, current flows from the source to the load through one conductor and returns via a ground plane or wire. The transversal electromagnetic wave (TEM), created by the current flow, can freely radiate to the outside environment causing severe electromagnetic interference (EMI).

FIG 3. TEM wave radiation from the large fringing fields around a single conductor and the small fringing fields outside the closely coupled conductor loop of a differential signal pair.

Also noise from external sources induced into the conductor is unavoidably amplified by the receiver, thus compromising signal integrity.

Differential signalling instead uses two conductors, one for the forward, the other one for the return current to flow. Thus, when closely coupled, the currents in the two conductors are of equal amplitude but opposite polarity and their magnetic fields cancel.

The TEM waves of the two conductors, now being robbed of their magnetic fields, cannot radiate
into the environment. Only the far smaller fringing fields outside the conductor loop can radiate, thus yielding significantly lower EMI (see Figure 3).

Another benefit of close electric coupling is that external noise induced into both conductors
equally appears as common- mode noise at the receiver input. Receivers with differential inputs are sensitive to signal differences only, but immune to common-mode signals. The receiver, therefore, rejects common- mode noise and signal integrity is maintained.

To make differential signalling work on a PCB, the spacing of the two traces of a differential
signal pair must be kept the same across the entire length of the trace. Otherwise, variations in
the spacing cause imbalances in the field coupling, thus, reducing the cancellation of the magnetic
fields “ leading to increased EMI. In addition to larger EMI, changes in conductor spacing cause the differential impedance of the signal pair to change, thus creating discontinuities in an
impedance-controlled transmission system, which leads to signal reflections compromising
signal integrity.

Besides consistent spacing, both conductors must be of equal electrical length to ensure their signals reach the receiver inputs at the same time. Figure 4 shows the “+” and the “”” signals of a differential pair during logic state changes for traces of equal and different length.

FIG 4. Traces of different electrical length cause phase shifts between signal, generating difference signals that cause serious EMI problems.

For traces of equal length both signals are equal and opposite. Therefore, their sum must add to zero. If the traces differ in electrical length, the signal on the shorter trace changes its state earlier than the one on the longer trace. During that time both traces drive currents into the same direction. Because the longer trace, which is supposed to act as return path, continues to drive current, the current of the “early” driving, shorter trace must find its return path via a reference plane (power or ground).

When adding both signals the sum signal diverts from the zero level during the transition phase. At high frequency these different signals appear as sharp transients of considerable magnitude, showing up on the ground plane, causing serious EMI problems.

Note that the width of the “noise” pulses is equal to the phase shift between the two signals, and can be translated into a time difference for a given frequency. This time difference, also known as intra-pair skew, is specified by HDMI for a receiver with 0.4 TBIT for a TMDS clock rate of 225 MHz, which translates to 178 ps maximum. For an HDMI transmitter the specification calls for 0.15 TBIT for a TMDS clock rate of 225 MHz, which translates to 66 ps maximum.

Because pixel generation requires the synchronous transmission of four differential TMDS signal pairs, (3 data + 1 clock), it must reach the receiver at the same time. Ideally, all four signal pairs should be of equal electrical length to ensure zero time difference. HDMI, however, allows
for a maximum inter-pair skew, the time difference between signal pairs, for a receiver of 0.2 TCHARACTER + 1.78 ns, yielding a total of 2.67 ns for a TMDS clock of 225 MHz. For an HDMI transmitter, the specification calls for 0.2 TCHARACTER resulting in 888ps.