Touch Sensor PCB and Layout Guidelines Part 2

PCB Layout Tips
This section provides guidelines on the design and layout related to several types of PCBs. See Figure 8.
The important task in PCB design is to draw sensor lines to reduce influence from internal and/or external noise sources. The types of noise sources and suggested design guidelines are described next.

Single Layer PCB Construction

A capacitive touch module can be designed in a singlelayer FR4 PCB of standard thickness (1.6mm). See Figure 9. The electrode and all the components are on the same side of the PCB. The other side of the PCB is attached to the overlay panel. The field senses through the PCB, the adhesive layer and the overlay panel to the finger. A one-layer PCB provides a less-costly solution compared to touch modules using more than one layer. However, the touch module using a one-layer PCB can only be implemented if there is enough area on the PCB for the
routing of the signals. Since the sensor electrode is placed at the bottom of the PCB, the sense field passes through the PCB and overlay panel before reaching the finger. In this case, the maximum overlay panel thickness is reduced due to the additional thickness of the PCB. The distance between the sensor electrode and touch sensor controller should be less than 5 inches to avoid excessive parasitic capacitance.
Single Layer PCB Design Rules

Layer 1 – Top layer design Tips

• Only the bottom layer is used and the top layer is empty. Non-conductive adhesive is to be applied on the top layer to attach the PCB to the overlay pane

Layer 2 – Bottom Layer design Tips

• Maximize the distance between one sensor electrode/ trace to the others in order to minimize crosstalk.
• For good sensitivity it is recommended to have a 6 x 6mm sensor area. It is still possible to utilize a sensor area smaller than this, but with reduced sensitivity. However, it is recommended that the sensor size is not larger than 10 x 10mm. If the sensor size is increased beyond this size, sensitivity will not increase as much as expected but the susceptibility to noise will increase substantially.
• The sensor signal traces do not need to be the same length. Input tuning capacitors are used to balance input capacitance between channels. However, if there is enough space on the PCB, balancing between the sensor input traces length can be done (sensor electrode size is uniform). In the latter case, only a reference tuning capacitor should be added in order to adjust all of the sensors’ impedance values to be in the center of the dynamic range.
• Any clock, data or periodic signal should not be routed side by side with the sensor signal traces. As much as possible these signals should be routed perpendicular with respect to the sensor signals. If they have to run in parallel, route them on a different cross section area of the PCB.

Two Layer PCB construction

In the 2-layer PCB construction, the touch sensor controller and other components are placed at the bottom layer of the PCB. See Figure 10 on the next page. The touch sensor electrodes are placed on the top layer. The distance between sensor electrodes and the controller
should be less than 5 inches to avoid excessive parasitic capacitance.
The tuning capacitor of each sensor channel can be placed directly underneath the sensor electrode itself. However, it is recommended to place the touch sensor controller at the bottom layer area where there is no touch sensor electrode on top.

Two Layer PCB Design Tips Layer 1 – Top Layer

The sensor electrodes are on the top layer of the PCB (top side of the PCB is to be attached to the overlay panel). For good sensitivity it is recommended to have 6 x 6mm sensor area. It is still possible to utilize a sensor area smaller than this, but with reduced sensitivity. However, it is recommended that the sensor size is not larger than 10 x 10mm. If the sensor size is increased beyond this size, sensitivity will not increase as much as expected but susceptibility to noise will increase substantially.

• The top layer can be used to route signal traces with the exception of sensor signal traces. As much as possible, sensor signal traces are to be routed at the bottom layer.

Layer 2 – Bottom Layer

• The touch sensor controller and passive components are to be placed at the bottom layer.
• Controller sensor signal traces are to be routed on the bottom layer. Sensor signal traces of a particular channel should not be routed underneath the sensor electrode of other channels.

• Maximize the distance between one sensor electrode/trace to the other in order to minimize crosstalk.
• Sensor signal traces do not need to be the same length. Input tuning capacitors are used to balance input capacitance between channels. However if space on the PCB allows, balancing sensor input traces length can be done (sensor electrodes size is uniform). In the latter case, only the reference tuning capacitor should be added in order to adjust all sensor impedance values to be in the center of the dynamic range.
• Any clock, data or periodic signal should not be routed side by side with the sensor signal traces. As much as possible these signals should be routed perpendicular with respect to the sensor signals or they should be routed on different area of the PCB.
• If clock, data, or any periodic signal traces should run in parallel proximity to sensor signal traces, they should be routed in a different layer and should not overlap. Keep the section where the signals run in parallel as short as possible.

Touch Sensor PCB and Layout Guidelines Part 1

Gigabit Ethernet Controller Design Guidelines --> Power and Ground Planes Considerations

The RJ-45 chassis ground and the digital ground should be isolated through a 1M Ohm resistor and a 0.1uF decoupling capacitor. And the gap between the chassis ground and digital ground must be wider than 60 mils.



All the digital and analog power planes for different voltage supplies should be isolated.




Note:

1. The above figures are the Digital Power (VDDxx) and Analog Power (AVDDxx) planes diagram of an illustrative LAN board design. For exact layout pattern, ASIX Electronics provides some demo boards and the layout PCB files and Gerber files for customer reference.
2. VDDK: Digital Core Power 2.5V
3. VDD2: Digital I/O Power 2.5V
4. AVDDK: Analog Core Power 2.5V

Provide a power plane right underneath the ASIX Ethernet controller such that the VCC pins can be contacted to the power plane without going through thin traces.


All power pins should be implemented with a decoupling capacitor, and the decoupling capacitor should be as close to the respective power pin of ASIX Ethernet controller as possible.

Gigabit Ethernet Controller Design Guidelines --> Ethernet Magnetic Selection Considerations

The Ethernet magnetic is dependent on the external PHY. Please refer to the external PHY’s datasheet and reference schematic for the detailed requirement of the Ethernet magnetic.



The following is the reference Ethernet magnetic circuit (single RJ-45 connector integrated 10/100/1000M Base-T magnetic with Turns Ratio 1CT:1CT and Auto-MDIX function) Gigabit PHY demo board.



4-Layer PCB Design

We strongly suggest customers to design to Gigabit Ethernet controller on the printed circuit board (PCB) with at least 4 layers. The 4-layer PCB design can help reduce some potential EMI, thermal and signal integrity issues, etc.

The following is an example 4-Layer PCB design for an embedded system application that uses Gigabit Ethernet controller.

PCB Stackup and Reference Planes PCI Express

PCI Express requires no new technology. Generally desktop system boards are designed with 4-layer stackup, whereas server, workstation, and mobile system boards use 6-layer stackup or greater. Add-in cards may use either 4-layer or 6-layer stackup. ½ oz copper plated microstrip and 1 oz copper stripline are used.

An add-in card is required to have overall board thickness of 0.062 inches. A mobile platform can have a thickness of 0.062 inches or 0.050 inches.

To minimize loss and jitter, the most important considerations are to design to a target impedance and to keep tolerances small. Thicker dielectrics and wider traces will minimize loss. Microstrip differential traces produce greater impedance variation than stripline traces.
A signal pair should avoid discontinuities in the reference plane, such as splits and voids. When a signal changes layers, the ground stitching vias should be placed close to the signal vias. A minimum of 1 to 3 stitching vias per pair of signals is recommended. Never route a trace so that it straddles a plane split.