POWER SUPPLY LAYOUT for RF Consideration

The most important requirement for the RF receiver modules to perform a wide range is a very stable and low noise supply voltage output. As important as the choice of power supply type and components is the design of the PCB to which these items are attached with regard to control both radiated and conducted emissions. The following recommendations apply also for designing the layout for additional electronics like digital circuits.

Since parasitic impedances increase with frequency, a simple PCB signal trace might become a complex path (antenna!), rather than just a low resistance with respect to DC measurements. Due to these parasitic impedances – both capacitive and inductive in nature, the layout of the PCB is very critical for the entire system.

Notes for Components Placement
1. Keep ground return paths short and wide. Provide a return path that creates the smallest loop for the current to return.

2. When routing the circuitry the analog small signal ground and the digital and power ground for switching currents must be kept separate.



3. It is suggested to isolate the analog circuitry on a local ground island, which can then be connected to the rest of the system ground at one single point. This helps to keep the analog ground clean and quiet. All connections between the analogue and digital circuitry should cross nearby single point.

Some general board layout guidelines
1. Use a multilayer PCB with separate GND and VCC planes. Keep connections between each supply pin and the corresponding power/ground plane as short as possible.

2. Try to make signal ground connections through Vias to the ground plane rather than through PCB traces. Any PCB trace acts as a transmit antenna.

3. Try to keep power ground, digital ground and analog ground separately. Tie the different grounds together (if they are electrically connected) at one single point near DC output return. Star grounding should be used whenever possible, as opposed to daisy chain grounding.

4. Minimize areas and lengths of loops which conduct high frequency switching currents see picture below. Magnetic coupling is a strong function of the loop area and is difficult to counteract, because a magnetic shield is usually required instead of simple copper shielding. Since PCBs use copper conductors, the traces and ground planes may be ineffective as shields against magnetic coupling.



5. Loop areas can be reduced by shortening the trace lengths and by routing signal traces next to their return paths, parallel to each other on adjacent layers. Loop areas can also be reduced by placing bypass capacitors as close to the noise source as possible.

6. Applicable to oscillators: if possible use a frequency (& harmonics) that falls outside the receiver working frequencies. Provide a guard ring tied to correspondingly ground for oscillator. Avoid routing below oscillator, area around and between oscillator and tracks filled with copper, Vias to appropiate ground.

7. DC/DC-converters particularly carry high frequency switching currents. For more information, please check individual manufacturer datasheets when using such components.

8. Place the filter capacitors so that their terminals are directly connected to the PCB traces that carry main current to be filtered (no extra trace length).

9. Keep the distance between the converter and the filter capacitors as short as possible to reduce parasitic effects and transient current flow.

10. Pick the smallest package for a given capacitance. Physically small capacitors tend to have lower parasitic inductance than physically large ones.

11. Also, a short capacitor has less inductance than a long capacitor, and a high profile capacitor has less inductance than a low profile capacitor. Use at least two capacitors which differ by a factor 100 in value to decouple. The reactance of large capacitors has a significant inductive component at higher frequencies.

12. Because of its inherent inductive component, a single large capacitor is not very effective against high frequency noise. Using paralleled capacitors like Tantalum (e.g. 22μF) in combination with ceramic capacitors (e.g. 0.1μF) reduces filter impedance across a wide frequency band see picture below. Among the paralleled capacitors: Place the ceramic capacitors closest to the device pin.

13. When laying out the PCB, always make provisions for as many noise suppression capacitors as possible. Consider this as risk reduction for the debug phase of your design. If the capacitors are not needed, just leave them out when the board is assembled.

14. For heavy environments you may also consider the use of shield planes and discrete inductors like ferrite beads or common mode chokes inserted into the signal or power line paths. Their handling requires however some experience.

15. If possible use a Spectral analyzer and a near field probe set to identify the interferences and their sources on PCB.

Analog, PLL, and Digital Power Supply Filtering

To minimize EMI emissions, add decoupling capacitors with a ferrite bead at power supply terminals for the analog, phase-locked loop (PLL), and digital portions of the chip. Place this array as close to the chip as possible to minimize the inductance of the line and noise contributions to the system. An analog and digital supply example is shown below. In case of multiple power supply pins with the same function, tie them up to a single low-impedance point in the board and then add the decoupling capacitors, in addition to the ferrite bead. This array of caps and ferrite bead improve EMI and jitter performance. Take both EMI and jitter into account before altering the configuration.


Consider the recommendations listed below to achieve proper ESD/EMI performance:

1. Use a 0.01 mF cap on each cable power VBUS line to chassis GND close to the USB connector pin.
2. Use a 0.01 mF cap on each cable ground line to chassis GND next to the USB connector pin.
3. If voltage regulators are used, place a 0.01 mF cap on both input and output. This is to increase the immunity to ESD and reduce EMI. For other requirements, see the device-specific datasheet.

Analog, Digital, and PLL Partitioning



If separate power planes are used, they must be tied together at one point through a low-impedance bridge or preferably through a ferrite bead. Care must be taken to capacitively decouple each power rail close to the device. The analog ground, digital ground, and PLL ground must be tied together to the low-impedance circuit board ground plane.

Clock Routings

To address the system clock emissions between devices, place a ~10 to 130 W resistor in series with the clock signal. Use a trial and error method of looking at the shape of the clock waveform on a high-speed oscilloscope and of tuning the value of the resistance to minimize waveform distortion. The value on this resistor should be as small as possible to get the desired effect. Place the resistor close to the device generating the clock signal.

When routing the clock traces from one device to another, try to use the 3W spacing rule. The distance from the center of the clock trace to the center of any adjacent signal trace should be at least three times the width of the clock trace. Many clocks, including slow frequency clocks, can have fast rise and fall times. Using the 3W rule cuts down on crosstalk between traces. In general, leave space between each of the traces running parallel between the devices. Avoid using right angles when routing traces to minimize the routing distance and impedance discontinuities. For further protection from crosstalk, run guard traces beside the clock signals (GND pin to GND pin), if possible. This lessens clock signal coupling, as shown below.