Most Important EMC Design Guidelines

Minimize the loop areas associated with high-frequency power and signal currents.

This simple rule is on nearly everybody's list of EMC guidelines, but it often gets ignored or compromised in favor of other guidelines. Often the board designer doesn't even know where the signal currents flow. Digital circuit designers like to think of signals in terms of their voltage. Signal integrity and EMC engineers must think of signals in terms of their current.

There are two things that every good circuit designer should know about signal currents.

1. Signal currents always return to their source (i.e. current paths are always loops)
2. Signal currents take the path(s) of least impedance.

At megahertz frequencies and higher, signal current paths are relatively easy to identify. This is because the path of least impedance at high frequencies is generally the path of least inductance, which is generally the path that minimizes the loop area. Currents return as close as possible to the path of the outgoing current. At low frequencies (generally kHz frequencies and below), the path of least impedance tends to be the path(s) of least resistance. Low frequency currents are more difficult to trace, since they will spread out. Significant current return paths may be relatively distant from the outgoing current path.

Don't Split, Gap or Cut the Signal Return Plane

Sure, there are some situations where a well-placed gap in the return plane is called for. However, these are relatively rare and always involve a need to control the flow of low-frequency currents. The safest rule-of-thumb is to provide one solid plane for returning all signal currents. In situations where you expect that a particular low-frequency signal is susceptible or is capable of interfering with the circuitry on your board, use a trace on a separate layer to return that current to its source. In general, never split, gap or cut your board's signal return plane. If you are convinced that a gap is necessary to prevent a low-frequency coupling problem, seek advice from an expert. Don't rely on design guidelines or application notes and don't try to implement a scheme that "worked" in someone else's "similar" design.



Don't Locate High-Speed Circuitry between Connectors

Among board designs that we have reviewed or evaluated in our lab, this is one of the most common problems we've encountered. Many times simple board designs that should have had no trouble at all meeting EMC requirements at no additional cost or effort, wind up being heavily shielded and filtered because they violated this simple rule.

Why is the location of connectors so important? At frequencies below a few hundred megahertz, wavelengths are on the order of a meter or longer. Any possible antennas on the printed circuit board itself tend to be electrically small and therefore inefficient. However, cables or other devices connected to a board can serve as relatively efficient antennas.

Signal currents flowing on traces and returning through solid planes result in small voltage differences between any two points on the plane. These voltage differences are generally proportional to the current flowing in the plane. When all connectors are placed along one edge of a board, the voltage between them tends to be negligible. However, high-speed circuitry located between connectors can easily develop potential differences of a few millivolts or greater between the connectors. These voltages can drive currents onto attached cables causing a product to exceed radiated emissions requirements.

Control Signal Transition Times

A board operating with a clock speed of 100 MHz should never fail to meet a radiated emissions requirement at 2 GHz. A well-formed digital signal will have a significant amount of power in the lower harmonic frequencies, but not so much power in the upper harmonics. Power in the upper harmonic frequencies is best controlled by controlling the transition times in digital signals. Longer transition times are preferred for EMC. Excessively long transition times can cause signal integrity and thermal problems. An engineering compromise must be reached between these competing requirements. A transition time that is approximately 20% of a bit period results in a reasonably good-looking waveform, while minimizing problems due to crosstalk and radiated emissions. Depending on the application, transitions times may need to be more or less than 20% of the bit period, however transitions times should not be left to chance.

There are three common methods for controlling rise and fall times in digital logic.

1. Use a logic family that is only as fast as the application requires.
2. Put a resistor or a ferrite in series with a device's output.
3. Put a capacitor in parallel with a device's output.

The first choice is often the easiest and most effective option. However, the use of a resistor or ferrite gives the designer more control and is less affected by changes that occur in logic families over time. Capacitors can actually increase the amount of high-frequency current drawn by the source device and in most cases are not an appropriate choice.

Note that it is never a good idea to try to slow down or filter a single-ended signal by impeding the flow of current in the return path. For example, one should never intentionally route a low-speed trace over a gap in a return plane in an attempt to filter out the high-frequency noise. After reviewing the first two design guidelines, this should be obvious. Nevertheless, boards employing this flawed design strategy occasionally show up in our lab.

SIGNAL INTEGRITY

In the realm of high-speed digital design, signal integrity has become a critical issue, and is posing increasing challenges to the design engineers. Many signal integrity problems are electromagnetic phenomena in nature and hence related to the EMI/EMC discussions in the previous sections of this blog. We will discuss what the typical signal integrity problems are, where they come from, why it is important to understand them and how we can analyze and solve these issues. Several software tools available at present for signal integrity analysis and current trends in this area will also be introduced.

The term Signal Integrity (SI) addresses two concerns in the electrical design aspects – the timing and the quality of the signal. Does the signal reach its destination when it is supposed to? And also, when it gets there, is it in good condition? The goal of signal integrity analysis is to ensure reliable high-speed data transmission. In a digital system, a signal is transmitted from one component to another in the form of logic 1 or 0, which is actually at certain reference voltage levels. At the input gate of a receiver, voltage above the reference value Vih is considered as logic high, while voltage below the reference value Vil is considered as logic low. Picture - 1 shows the ideal voltage waveform in the perfect logic world, whereas Picture - 2 shows how signal will look like in a real system. More complex data, composed of a string of
bit 1 and 0s, are actually continuous voltage waveforms. The receiving component needs to sample the waveform in order to obtain the binary encoded information. The data sampling process is usually triggered by the rising edge or the falling edge of a clock signal as shown in the Picture 3. It is clear from the diagram that the data must arrive at the receiving gate on time and settle down to a non-ambiguous logic state when the receiving component starts to latch in. Any delay of the data or distortion of the data waveform will result in a failure of the data transmission. Imagine if the signal waveform in Picture - 2 exhibits excessive ringing into the logic gray zone while the sampling occurs, then the logic level cannot be reliably detected.

Picture 1



Picture 2

Picture 3

Typical SI Problems

“Timing” is everything in a high-speed system. Signal timing depends on the delay caused by the physical length that the signal must propagate. It also depends on the shape of the waveform when the threshold is reached. Signal waveform distortions can be caused by different mechanisms. But there are three mostly concerned noise problems:

--> Reflection Noise
Due to impedance mismatch, stubs, vias and other interconnect discontinuities.

--> Crosstalk Noise
Due to electromagnetic coupling between signal traces and vias.

--> Power/Ground Noise
Due to parasitics of the power/ground delivery system during drivers’ simultaneous switching output (SSO). It is sometimes also called Ground Bounce, Delta-I Noise or Simultaneous Switching Noise (SSN).

Besides these three kinds of SI problems, there are other Electromagnetic Compatibility or Electromagnetic Interference (EMC/EMI) problems that may contribute to the signal waveform distortions. When SI problems happen and the system noise margin requirements are not satisfied – the input to a switching receiver makes an inflection below Vih minimum or above Vil maximum; the input to a quiet receiver rises above Vil maximum or falls below Vih minimum; power/ground voltage fluctuations disturb the data in the latch, then logic error, data drop, false switching, or even system failure may occur. These types of noise faults are extremely difficult to diagnose and solve after the system is built or prototyped. Understanding and solving these problems before they occur will eliminate having to deal with them further into the project cycle, and will in turn cut down the development cycle and reduce the cost. In the later part of this chapter, we will have further investigations on the physical behavior of these noise phenomena, their causes, their electrical models for analysis and simulation, and the ways to avoid them.

Where SI Problems Happen

Since the signals travel through all kinds of interconnections inside a system, any electrical impact happening at the source end, along the path, or at the receiving end, will have great effects on the signal timing and quality. In a typical digital system environment, signals originating from the off-chip drivers on the die (the chip) go through c4 or wire-bond connections to the chip package. The chip package could be single chip carrier or multi-chip module (MCM). Through the solder bumps of the chip package, signals go to the Printed Circuit Board (PCB) level. At this level, typical packaging structures include daughter card, motherboard or backplane. Then signals continue to go to another system component, such as an ASIC (Application Specific Integrated Circuit) chip, a memory module or a termination block. The chip
packages, printed circuit boards, as well as the cables and connecters, form the so-called ifferent levels of electronic packaging systems, as illustrated in below. In each level of the packaging structure, there are typical interconnects, such as metal traces, vias, and power/ground planes, which form electrical paths to conduct the signals. It is the packaging interconnection that ultimately influences the signal integrity of a system.


SI In Electronic Packaging

Technology trends toward higher speed and higher density devices have pushed the package performance to its limits. The clock rate of present personal computers is approaching gigahertz range. As signal risetime becomes less than 200ps, the significant frequency content of digital signals extends up to at least 10 GHz. This necessitates the fabrication of interconnects and packages to be capable of supporting very fast varying and broadband signals without degrading signal integrity to unacceptable levels. While the chip design and fabrication technology have undergone a tremendous evolution: gate lengths, having scaled from 50 μm in the 1960s to 0.18 μm today, are projected to reach 0.1 μm in the next few years; on-chip clock frequency is doubling every 18 months; and the intrinsic delay of the gate is decreasing exponentially with time to a few tens of pico-seconds. However, the package design has lagged considerably. With current technology, the package interconnection delay dominates the system timing budget and becomes the bottleneck of the high-speed system design. It is generally accepted today that package performance is one of the major limiting factors of the overall system performance.

Advances in high performance sub-micron microprocessors, the arrival of gigabit networks, and the need for broadband Internet access, necessitate the development of high performance packaging structures for reliable high-speed data transmission inside every electronics system. Signal integrity is one of the most important factors to be considered when designing these packages (chip carriers and PCBs) and integrating these packages together.