Analog, PLL, and Digital Power Supply Filtering

To minimize EMI emissions, add decoupling capacitors with a ferrite bead at power supply terminals for the analog, phase-locked loop (PLL), and digital portions of the chip. Place this array as close to the chip as possible to minimize the inductance of the line and noise contributions to the system. An analog and digital supply example is shown below. In case of multiple power supply pins with the same function, tie them up to a single low-impedance point in the board and then add the decoupling capacitors, in addition to the ferrite bead. This array of caps and ferrite bead improve EMI and jitter performance. Take both EMI and jitter into account before altering the configuration.


Consider the recommendations listed below to achieve proper ESD/EMI performance:

1. Use a 0.01 mF cap on each cable power VBUS line to chassis GND close to the USB connector pin.
2. Use a 0.01 mF cap on each cable ground line to chassis GND next to the USB connector pin.
3. If voltage regulators are used, place a 0.01 mF cap on both input and output. This is to increase the immunity to ESD and reduce EMI. For other requirements, see the device-specific datasheet.

Analog, Digital, and PLL Partitioning



If separate power planes are used, they must be tied together at one point through a low-impedance bridge or preferably through a ferrite bead. Care must be taken to capacitively decouple each power rail close to the device. The analog ground, digital ground, and PLL ground must be tied together to the low-impedance circuit board ground plane.

Clock Routings

To address the system clock emissions between devices, place a ~10 to 130 W resistor in series with the clock signal. Use a trial and error method of looking at the shape of the clock waveform on a high-speed oscilloscope and of tuning the value of the resistance to minimize waveform distortion. The value on this resistor should be as small as possible to get the desired effect. Place the resistor close to the device generating the clock signal.

When routing the clock traces from one device to another, try to use the 3W spacing rule. The distance from the center of the clock trace to the center of any adjacent signal trace should be at least three times the width of the clock trace. Many clocks, including slow frequency clocks, can have fast rise and fall times. Using the 3W rule cuts down on crosstalk between traces. In general, leave space between each of the traces running parallel between the devices. Avoid using right angles when routing traces to minimize the routing distance and impedance discontinuities. For further protection from crosstalk, run guard traces beside the clock signals (GND pin to GND pin), if possible. This lessens clock signal coupling, as shown below.

USB 2.0 Differential Trace DP/DM and Crystal Oscillator

USB 2.0 Differential Trace DP/DM

Place the USB PHY as close as possible to the USB 2.0 connector. The signal swing during high-speed operation on the DP/DM lines is relatively small (400 mV ± 10%), so any differential noise picked up on the twisted pair can affect the received signal. When the DP/DM traces do not have any shielding, the traces tend to behave like an antenna and picks up noise generated by the surrounding components in the environment. To minimize the effect of this behavior:

1. DP/DM traces should always be matched lengths and must be no more than 4 inches in length; otherwise, the eye opening may be degraded as shown below.
2. Route DP/DM traces close together for noise rejection on differential signals, parallel to each other and within two mils in length of each other (start the measurement at the chip package boundary, not to the balls or pins).
3. A high-speed USB connection is made through a shielded, twisted pair cable with a differential characteristic impedance of 90 W ±15%. In layout, the impedance of DP and DM should each be 45 W ± 10%.
4. DP/DM traces should not have any extra components to maintain signal integrity. For example, traces cannot be routed to two USB connectors.

DP/DM Vias

When a via must be used, increase the clearance size around it to minimize its capacitance. Each via introduces discontinuities in the signal’s transmission line and increases the chance of picking up interference from the other layers of the board. Be careful when designing test points on twisted pair lines; through-hole pins are not recommended.

Crystals / Oscillator

Keep the crystal and its load capacitors close to the USB PHY pins, XI and XO (see Figure 5). Note that frequencies from power sources or large capacitors can cause modulations within the clock and should not be placed near the crystal. In these instances, errors such as dropped packets occur. A placeholder for a resistor, in parallel with the crystal, can be incorporated in the design to assist oscillator startup.

Power is proportional to the current squared. The current is I = C*dv/dt, since dv/dt is a function of the PHY, current is proportional to the capacitive load. Cutting the load to decreases the current by and the power to 1/4 the original value.

Image Plance for USB 2.0

An image plane is a layer of copper (voltage plane or ground plane), physically adjacent to a signal routing plane. Use of image planes provides a low impedance, shortest possible return path for RF currents. For a USB board, the best image plane is the ground plane because it can be used for both analog and digital circuits.

1. Do not route traces so they cross from one plane to the other. This can cause a broken RF return path resulting in an EMI radiating loop as shown below. This is important for higher frequency or repetitive signals. Therefore, on a multi-layer board, it is best to run all clock signals on the signal plane above a solid ground plane.
2. Avoid crossing the image power or ground plane boundaries with high-speed clock signal traces immediately above or below the separated planes. This also holds true for the twisted pair signals (DP,DM). Any unused area of the top and bottom signal layers of the PCB can be filled with copper that is connected to the ground plane through vias.

Do not overlap planes that do not reference each other. For example, do not overlap a digital power plane with an analog power plane as this produces a capacitance between the overlapping areas that could pass RF emissions from one plane to the other, as shown in below.



Avoid image plane violations. Traces that route over a slot in an image plane results in a possible RF return loop, as shown in below.

Component Placement

Components on a PCB operate a variety of edge rates and have varying levels of tolerance to noise. The most straightforward method for improving SI is to physically isolate components on the PCB according to their edge rates and sensitivity. An example is shown below. In this example, the power supply, digital I/O and high-speed logic are considered to be high-threat circuits to the sensitive clock and data converter circuits.


The first layout in above picture places the clocks and data converters adjacent to noisy components. Noise will be coupled into the sensitive circuits and their performance will be compromised. The second layout is much better as the sensitive circuits are physically isolated from the power supply, high-speed logic and digital I/O.