Hardware and Layout Design Considerations for DDR2 SDRAM Memory Interfaces -- Designer’s Checklist

The design guidelines presented in this document apply to products that leverage the DDR2 SDRAM IP core, and they are based on a compilation of internal platforms.

The purpose of these guidelines is to minimize board-related issues across multiple memory topologies while allowing maximum flexibility for the board designer.

Because numerous memory topologies and interface frequencies are possible on the DDR2 SDRAM interface, It is highly recommends that the system/board designer verify all design aspects (signal integrity, electrical timings, and so on) through simulation before PCB fabrication.

Designer’s Checklist

In the following checklist, some of the items are phrased as question, others as requirements. In all cases, we recommend that you consider the line items

Simulation

1. Have optimal termination values, signal topology, trace lengths been determined through simulation for each signal group in the memory implementation? If on-die termination is used at both the memories and the controller, no additional termination is required for the data group.

Four unique groupings exist:

• Data Group: MDQS(8:0), MDQS(8:0), MDM(8:0), MDQ(63:0), MECC(7:0)
• Address/CMD Group: MBA(2:0), MA(15:0), MRAS, MCAS, MWE.
• Control Group: MCS(3:0), MCKE(3:0), MODT(3:0)
• Clock Group: MCK(5:0) and MCK(5:0)

These groupings assume a full 72-bit data implementation (64-bit + 8 bit of ECC. Some products may only implement 32-bit data and may choose to have less MCS MCKE, and MODT signals. Secondly, some products support the optional MAPAR_OUT and MAPAR_ERR for registered DIMMs. In such cases, MAPAR_OUT should be treated as part of the ADDR/CMD group and MAPAR_ERR can be treated as an asynchronous signal.

2. Does the selected termination scheme meet the AC signaling parameters (voltage levels, slew rate, overshoot/undershoot) across all memory chips in the design?

Termination Scheme

It is assumed that the designer is using the mainstream termination approach as found in commodity PC motherboards. Specifically, it is assumed that on-die termination is used for the data groups and that external parallel resistors tied to VTT are used for the Address/CMD and the control groups. Consequently, differing termination techniques may also prove valid and useful. However, they are left to the designer to validate through simulation.

1. Is the worst case power dissipation for the termination resistors within the manufacturer’s rating for the selected devices?
2. If resistor packs are used, have data lanes been isolated from the other DDR2 signal groups? Note: Because on-die termination is the preferred method for DDR2 data signals, external resistors for the data group should not be required. This item would only apply if the ODT feature is not used.
3. Have VTT resistors been properly placed? The RT terminators should directly tie into the VTT island at the end of the memory bus.
4. If series damping (RS) terminators are used (not seen as mainstream approach), were they placed close to the first memory DIMM? For discrete implementations—Placement of the series damping resistor (RS) for the data group is left to the board designer. This trade-off is optimal signal integrity for both reads/writes (RS in middle) versus ease of layout routing (RS placed closer to memory devices).
5. For address and command signals, the Micron compensation cap scheme is another optional
6. termination method for improving eye apertures for a heavily loaded system (> 18 memory chips). For details on this termination scheme refer to DDR533 Memory Design for Two-DIMM Unbuffered Systems, located on Micron’s web site. For lightly and medium loaded memory subsystems (4–18 chips), the compensation cap method is not as beneficial. If used, are the CCOMP capacitors placed within 0.5 inch of the first memory bank?
7. Is the differential terminator present on the clock lines for discrete memory populations? (DIMM modules contain this terminator.) Nominal range => 100-120 Ω.
8. Recommend that an optional 5pF cap be placed across each clock diff pair. If DIMM modules are used, the cap should be placed as closely as possible to the DIMM connector. If discrete devices are used, the cap should be placed as closely as possible to the discrete devices.
9. Recommendation—Place 0-Ω resistors on the DDR2 clock lines (near the driver). Such flexibility allows the clock lengths to be extended (if needed) during the prototyping phase.

VTT Related Items

1. Has the worst case current for the VTT plane been calculated based on the design termination scheme?
2. Can the VTT regulator support the steady state and transient current needs of the design?
3. Has the VTT island been properly decoupled with high frequency decoupling? At least 1 low ESL cap, or 2 standard decoupling caps for each 4-pack resistor network (or every 4 discrete resistors) should be used. In addition, at least one 4.7-μF cap should be at each end of the VTT island. Note: This recommendation is based on a top-layer VTT surface island (lower inductance). If an internal split is used, more capacitors may be needed to handle the transient current demands.
4. Has the VTT island been properly decoupled with bulk decoupling? At least 1 bulk cap (100–220 μF) capacitor should be at each end of the island.
5. Has the VTT island been placed at the end of the memory channel and as closely as possible to the last memory bank? Is the VTT regulator placed in close proximity to the island?
6. Is a wide surface trace (~150 mils) used for the VTT island trace?
7. If a sense pin is present on the VTT regulator, is it attached in the middle of the island?

VREF

1. Is VREF routed with a wide trace? (Minimum of 20–25 mil recommended.)
2. Is VREF isolated from noisy aggressors? In addition, maintain at least a 20–25 mil clearance from VREF to other traces. If possible, isolate VREF with adjacent ground traces.
3. Is VREF properly decoupled? Specifically, decouple the source and each destination pin with 0.1uf caps.
4. Does the VREF source track variations in VDDQ, temperature, and noise as required by the JEDEC specification?
5. Does the VREF source supply the minimal current required by the system (memories + processor)?
6. If a resistor divider network is used to generate VREF, are both resistors the same value and 1% tolerance?

Routing

Suggest routing order within the DDR2 interface: 1) Data, 2) Address/Command, 3) Control, 4) Clocks, and 5) Power This order allows the clocks to be tuned easily to the other signal groups. It also assumes an open critical layer on which clocks are freely routed.

Global items—Do not route any DDR2 signals overs splits or voids. Traces routed near the edge of a reference plane should maintain at least 30–40 mil gap to the edge of the reference plane.
Allow no more than 1/2 of a trace width to be routed over via antipad.

When routing the data lanes, route the outermost (that is, longest lane first) because this determines the amount of trace length to add on the inner data lanes.

Are the clock pair assignments optimized to allow break-out of all pairs on a single critical layer?

The DDR2 data bus consists of 9 data byte lanes (assuming ECC is used). All signals within a given byte lane should be routed on the same critical layer with the same via count.
Note: Some product implementations may only implement a 32-bit wide interface.

• Byte Lane 0—MDQ(7:0), MDM(0), MDQS(0), MDQS(0)
• Byte Lane 1—MDQ(15:8), MDM(1), MDQS(1), MDQS(1)
• Byte Lane 2—MDQ(23:16), MDM(2), MDQS(2), MDQS(2)
• Byte Lane 3—MDQ(31:24), MDM(3), MDQS(3), MDQS(3)
• Byte Lane 4—MDQ(39:32), MDM(4), MDQS(4), MDQS(4)
• Byte Lane 5—MDQ(47:40), MDM(5), MDQS(5), MDQS(5)
• Byte Lane 6—MDQ(55:48), MDM(6), MDQS(6), MDQS(6)
• Byte Lane 7—MDQ(63:56), MDM(7), MDQS(7), MDQS(7)
• Byte Lane 8—MECC(7:0), MDM(8), MDQS(8), MDQS(8)

To facilitate fan-out of the DDR2 data lanes (if needed), alternate adjacent data lanes onto different critical layers?

Note: If the device supports ECC, Freescale highly recommends that the user implement ECC on
the initial hardware prototypes.

DDR2 data group—Impedance range and spacing

• Single-ended target Impedance = 50–60 Ω range (MDQ, MDM)
• Differential target impedance = 100–120 Ω range (MDQS, MDQS) Note: Some product implementations may support only the single-ended version of the strobe.
• Referenced to a solid ground plane, thereby providing a low-impedance path for return currents.
• Trace space to other non-DDR2 data groups = 25 mil.
• Trace space requirements within the DDR2 data group = 10 mils (reducing to 7 mils inside the DIMM area). Note: Based on a trace width of 5 mil.

Across all DDR2 data lanes, are all the data lanes matched to within 0.5 inch?

Is each data lane properly trace matched to within 20 mils of its respective differential data strobe? (Assumes highest frequency operation.)

When adding trace lengths to any of the DDR2 signal groups, ensure that there is at least 25 mils between serpentine loops that are in parallel.

MDQS/MDQS differential strobe routing
Note: Some product implementations may support only the single-ended version of the strobe.

• Match all segment lengths between differential pairs along the entire length of the pair. Trace match the MDQS/ MDQS pair to be within 10 mils.
• Maintain constant line impedance along the routing path by maintaining the required line width and trace separation for the given stackup.
• Avoid routing differential pairs adjacent to noisy signal lines or high speed switching devices such as clock chips.
• Differential Impedance = 100–120 (50–60 Ω single ended with proper spacing)
• Do not divide the two halves of the diff pair between layers. Route MDQS/MDQS pair on the samecritical layer as its associated data lane.

DDR2 address/command group—Impedance range and spacing

• Single-Ended Target Impedance = 50–60 Ω range
• Match all traces to within 100 mils
• Referenced to a contiguous 1.8-V power reference (DIMM implementations currently do this)
• Referenced to a contiguous 1.8-V power reference or ground plane (discrete implementations)
• Trace space to other non-DDR2 address/cmd signals = 25 mil.
• Trace space requirements within the DDR2 address/cmd group = 10 mils (reducing to 7 mils inside the DIMM area). Note: Based on a trace width of 5 mil.

DDR2 control group—Impedance range and spacing

• Single-Ended Target Impedance = 50–60 Ω range
• Match all traces to within 100 mils
• Referenced to a contiguous 1.8-V power reference (DIMM implementations currently do this)
• Referenced to a contiguous 1.8-V power reference or ground plane (discrete implementations)
• Trace space to other non-DDR2 control groups = 25 mil.
• Trace space requirements within the DDR2 control group = 10 mils (reducing to 7 mils inside the DIMM area). Note: Based on a trace width of 5 mil.

Are the DDR2 signal groups tuned to the clock reference? Because this is loading and topology dependent, the variance around the clock should be determined by simulation. Secondly, in multi-bank systems, are the address and command signals loaded more heavily than the control signals (CS, ODT, CKE)?
Specifically:

• Are the setup/hold optimized for the addr/cmd group?
• Are the steup/hold optimized for the control group (CS, ODT, CKE)?
• Is the write data delay window met (tDQSS)? This is the relationship between the data strobes and clocks as specified by the JEDEC DDR2 specification.

Are the DDR2 differential clocks properly routed?

• Match all segment lengths between differential pairs along the entire length of the pair. Trace match the MCK/ MCK pair to be within 10 mils.
• Maintain constant line impedance along the routing path by maintaining the required line width and trace separation for the given stackup.
• Avoid routing differential pairs adjacent to noisy signals lines or high speed switching devices such as clock chips.
• Differential Impedance = 100–120 (50–60 Ω single ended with proper spacing)
• Do not divide the two halves of the diff pair between layers. Route MCK/MCK pair on the same critical layer.

Are all clock pairs routed on the same critical layer (one referenced to a solid ground plane)?

Are all clock pairs properly trace matched to within 25 mils of each other?

The space from one differential pair to any other trace (this includes other differential pairs) should be at least 25 mils.

If unbuffered DIMM modules are used, are all three required clock pairs per DIMM slot connected?

If the optional 0-Ω resistors are used (as noted in item 10), use ground stitching vias near the resistors.

MODT/MDIC Related Items

Are the MODT signals connected correctly?

• MODT(0), MCS(0), MCKE(0) should all go to the same physical memory bank.
• MODT(1), MCS(1), MCKE(1) should all go to the same physical memory bank.
• MODT(2), MCS(2), MCKE(2) should all go to the same physical memory bank.
• MODT(3), MCS(3), MCKE(3) should all go to the same physical memory bank.

Is MDIC0 connected to ground via an 18.2-Ω precision 1% resistor? Is MDIC1 connected to DDR
power via an 18.2-Ω precision 1% resistor?