Within a breakout area (for example, Philips PCI Express PHY ball field, connector pins, or add-in card edge fingers), exceptions to the general trace routing guidelines may occur.
5 mils intra-pair space and 10 mils inter-pair space are allowed in the breakout region. A small section of trace, up to 50 mils, does not necessarily require a reference plane. Length matching should occur as close as possible to signal pins without introducing any tight bends.
Picture shows some techniques used in breakout areas. Side-by-side placement is considered best. Adjacent with a small serpentine is acceptable. Diagonal routing and adjacent placement with a bend are acceptable but not as good as the other techniques.
This blog presents the most common design issues affecting signal integrity in high-speed digital hardware design. These include impedance control, terminations, ground/power planes, signal routing and crosstalk. Armed with the knowledge presented here, a digital designer will be able to recognize potential signal integrity problems at the earliest design stage. Also, they will be able to apply techniques presented to prevent these issues affecting the performance of their design.
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