Wednesday, June 24, 2009

General Routing Techniques with Emphasis on PI6C10X Clocks -- > Part 2

Solutions to Routing Problems

Reducing RF Currents

To provide an efficient path for RF currents to ground place a localized ground plane under the clock generator. The inside PCB ground plane could be two or three levels away and may not be sufficient for RF current path.

Xin and Xout Pins (focus on PI6C10X)

In the PI6C10X, the Xin and Xout pins are the input reference clocks. In the majority of designs, a parallel resonant quartz is connected to Xin and Xout pins. The device already includes the parasitic and loading capacitors that are connected to Xin and Xout and groumd. In designs where there is already a clock available, this clock signal is connected to Xin pin directly and Xout is left unconnected. The leads of the Crystal Oscillator connected to Xin and Xout pins should be as short as possible since the Xin pin is high impedance and is highly sensitive to noise. To prevent inductive and capacitive coupling any other clock signal should not be close to Xin and Xout signals.

Bypass Capacitors

To eliminate the majority of the noise, the design engineer must consider these steps. Each VDD should have a minimum of 0.1uF capacitor to ground to eliminate high frequency noise. Rising clock edges that cause current spikes from PCB Power and Ground planes causes the high frequency noise. To allow for better power bypassing, the power and ground should be as close as possible in the PCB layers. All decoupling capacitors must be placed on the same side as the component on the PCB. For the best performance, we strongly recommend high quality, monolithic, ceramic, surface mount capacitors with low ESR. These capacitors must be placed as close to the device pins as possible. As shown in picture below, typically a 0.1mF capacitor for every power supply pin of the clock generator is sufficient. However, for higher frequency noise, capacitors in the range of 200pF to 2.8nF are more suitable. The best performance is obtained with a large and small chip capacitor connected as closely as possible to the supply.

Noise Reduction Circuit

It is highly recommended to use a noise reduction circuitry on entering power supply line. This circuit consists of a resistor and a capacitor as shown in picture below. This circuit is used to decouple the power rail from the system supply. The resistor value should by around 2.7 ohms. This circuit in effect reduces the power supply variations that may cause destabilization. Destabilization usually presents itself in the form of Jitter. In the severest form it may even cause loss of PLL locking. In production, however, it is possible to remove this resistor if it does not cause problem. Tantalum capacitors with values between 10mFand 100mF can be used to eliminate power supply destabilization. This condition mainly is seen when the clock generator is switching all outputs at the same time with maximum capacitive load.

The switching noise generated by the clock generator should be decoupled to PCB ground planes. This noise is being radiated through the power connection to the board power supply. To block this high frequency noise and to accomplish this decoupling, tantalum capacitors and a Ferrite Bead are used to block the high frequency noise. The Ferrite Bead in essence isolates the main power plan of the board from the clock generator power plane. This method eliminates the noise generated by the clock generator from reaching the main power supply plain. A minimum of 1.7 Henries is recommended for this Ferrite Bead, however, the bigger the Ferrite Bead the better blocking is accomplished. Indeed, there is always a trade off with space. The Ferrite Bead must be capable of providing the rated DC current to the VCC plane. Also DC impedance of the Ferrite Bead must be very close to zero. The impedance of the Ferrite bead, however, at the clock frequency must be very high. This is typically greater than 50 ohms under loaded conditions with DC current flowing through it. With these conditions met, the Ferrite Bead will then present a large impedance at the clock frequency and will prevent noise due to clock harmonics from flowing to the PCB. Right picture shows the High Frequency Power Bypassing Schematic.

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