AC Coupling Capacitors for PCI Express

PCI Express requires AC coupling between transmitter and receiver. The AC coupling capacitors for both differential pair signals must be the same value, same package size, and have symmetric placement. If possible, TX traces should route on the top layer.

The capacitor value must be in the range of 75 nF to 200 nF (100 nF is best). The 0402 package size is preferred, and 0603 is acceptable. C-pack is not allowed.

The breakout into and out of capacitors should be symmetrical for both signal lines in a differential pair. The trace separation for routing to pads must be minimized in order to optimize tight coupling between the signal pairs.

Breakout Areas Considerations for PCI Express

Within a breakout area (for example, Philips PCI Express PHY ball field, connector pins, or add-in card edge fingers), exceptions to the general trace routing guidelines may occur.

5 mils intra-pair space and 10 mils inter-pair space are allowed in the breakout region. A small section of trace, up to 50 mils, does not necessarily require a reference plane. Length matching should occur as close as possible to signal pins without introducing any tight bends.

Picture shows some techniques used in breakout areas. Side-by-side placement is considered best. Adjacent with a small serpentine is acceptable. Diagonal routing and adjacent placement with a bend are acceptable but not as good as the other techniques.

PCI Express Width and Spacing

Coupling of the intra-pair differential signals and increased spacing to neighboring signals help to minimize harmful crosstalk impacts and Electro-Magnetic Interference (EMI) effects. In the microstrip case, a differential trace should be 5 mils wide, with a 7 mil wide air gap spacing between the two traces of a pair. Any uncoupled sections whose intra-pair space exceeds 7 mils can be routed as a 7 mil wide trace, if the section is 100 mils or longer. In the stripline case, a differential trace should be 5 mils wide with a 5 mil wide gap between the two traces of a pair.

The spacing between pairs and to all non-PCI Express signals should be 20 mils or four times the dielectric height, whichever is greater. If the non-PCI Express signals have significantly higher voltage levels or edge rate than the PCI Express signal, the space should increase to 30 mils in order to avoid coupling.

PCB Stackup and Reference Planes PCI Express

PCI Express requires no new technology. Generally desktop system boards are designed with 4-layer stackup, whereas server, workstation, and mobile system boards use 6-layer stackup or greater. Add-in cards may use either 4-layer or 6-layer stackup. ½ oz copper plated microstrip and 1 oz copper stripline are used.

An add-in card is required to have overall board thickness of 0.062 inches. A mobile platform can have a thickness of 0.062 inches or 0.050 inches.

To minimize loss and jitter, the most important considerations are to design to a target impedance and to keep tolerances small. Thicker dielectrics and wider traces will minimize loss. Microstrip differential traces produce greater impedance variation than stripline traces.
A signal pair should avoid discontinuities in the reference plane, such as splits and voids. When a signal changes layers, the ground stitching vias should be placed close to the signal vias. A minimum of 1 to 3 stitching vias per pair of signals is recommended. Never route a trace so that it straddles a plane split.