Hardware and Layout Design Considerations for DDR2 SDRAM Memory Interfaces -- Designer’s Checklist

The design guidelines presented in this document apply to products that leverage the DDR2 SDRAM IP core, and they are based on a compilation of internal platforms.

The purpose of these guidelines is to minimize board-related issues across multiple memory topologies while allowing maximum flexibility for the board designer.

Because numerous memory topologies and interface frequencies are possible on the DDR2 SDRAM interface, It is highly recommends that the system/board designer verify all design aspects (signal integrity, electrical timings, and so on) through simulation before PCB fabrication.

Designer’s Checklist

In the following checklist, some of the items are phrased as question, others as requirements. In all cases, we recommend that you consider the line items

Simulation

1. Have optimal termination values, signal topology, trace lengths been determined through simulation for each signal group in the memory implementation? If on-die termination is used at both the memories and the controller, no additional termination is required for the data group.

Four unique groupings exist:

• Data Group: MDQS(8:0), MDQS(8:0), MDM(8:0), MDQ(63:0), MECC(7:0)
• Address/CMD Group: MBA(2:0), MA(15:0), MRAS, MCAS, MWE.
• Control Group: MCS(3:0), MCKE(3:0), MODT(3:0)
• Clock Group: MCK(5:0) and MCK(5:0)

These groupings assume a full 72-bit data implementation (64-bit + 8 bit of ECC. Some products may only implement 32-bit data and may choose to have less MCS MCKE, and MODT signals. Secondly, some products support the optional MAPAR_OUT and MAPAR_ERR for registered DIMMs. In such cases, MAPAR_OUT should be treated as part of the ADDR/CMD group and MAPAR_ERR can be treated as an asynchronous signal.

2. Does the selected termination scheme meet the AC signaling parameters (voltage levels, slew rate, overshoot/undershoot) across all memory chips in the design?

Termination Scheme

It is assumed that the designer is using the mainstream termination approach as found in commodity PC motherboards. Specifically, it is assumed that on-die termination is used for the data groups and that external parallel resistors tied to VTT are used for the Address/CMD and the control groups. Consequently, differing termination techniques may also prove valid and useful. However, they are left to the designer to validate through simulation.

1. Is the worst case power dissipation for the termination resistors within the manufacturer’s rating for the selected devices?
2. If resistor packs are used, have data lanes been isolated from the other DDR2 signal groups? Note: Because on-die termination is the preferred method for DDR2 data signals, external resistors for the data group should not be required. This item would only apply if the ODT feature is not used.
3. Have VTT resistors been properly placed? The RT terminators should directly tie into the VTT island at the end of the memory bus.
4. If series damping (RS) terminators are used (not seen as mainstream approach), were they placed close to the first memory DIMM? For discrete implementations—Placement of the series damping resistor (RS) for the data group is left to the board designer. This trade-off is optimal signal integrity for both reads/writes (RS in middle) versus ease of layout routing (RS placed closer to memory devices).
5. For address and command signals, the Micron compensation cap scheme is another optional
6. termination method for improving eye apertures for a heavily loaded system (> 18 memory chips). For details on this termination scheme refer to DDR533 Memory Design for Two-DIMM Unbuffered Systems, located on Micron’s web site. For lightly and medium loaded memory subsystems (4–18 chips), the compensation cap method is not as beneficial. If used, are the CCOMP capacitors placed within 0.5 inch of the first memory bank?
7. Is the differential terminator present on the clock lines for discrete memory populations? (DIMM modules contain this terminator.) Nominal range => 100-120 Ω.
8. Recommend that an optional 5pF cap be placed across each clock diff pair. If DIMM modules are used, the cap should be placed as closely as possible to the DIMM connector. If discrete devices are used, the cap should be placed as closely as possible to the discrete devices.
9. Recommendation—Place 0-Ω resistors on the DDR2 clock lines (near the driver). Such flexibility allows the clock lengths to be extended (if needed) during the prototyping phase.

VTT Related Items

1. Has the worst case current for the VTT plane been calculated based on the design termination scheme?
2. Can the VTT regulator support the steady state and transient current needs of the design?
3. Has the VTT island been properly decoupled with high frequency decoupling? At least 1 low ESL cap, or 2 standard decoupling caps for each 4-pack resistor network (or every 4 discrete resistors) should be used. In addition, at least one 4.7-μF cap should be at each end of the VTT island. Note: This recommendation is based on a top-layer VTT surface island (lower inductance). If an internal split is used, more capacitors may be needed to handle the transient current demands.
4. Has the VTT island been properly decoupled with bulk decoupling? At least 1 bulk cap (100–220 μF) capacitor should be at each end of the island.
5. Has the VTT island been placed at the end of the memory channel and as closely as possible to the last memory bank? Is the VTT regulator placed in close proximity to the island?
6. Is a wide surface trace (~150 mils) used for the VTT island trace?
7. If a sense pin is present on the VTT regulator, is it attached in the middle of the island?

VREF

1. Is VREF routed with a wide trace? (Minimum of 20–25 mil recommended.)
2. Is VREF isolated from noisy aggressors? In addition, maintain at least a 20–25 mil clearance from VREF to other traces. If possible, isolate VREF with adjacent ground traces.
3. Is VREF properly decoupled? Specifically, decouple the source and each destination pin with 0.1uf caps.
4. Does the VREF source track variations in VDDQ, temperature, and noise as required by the JEDEC specification?
5. Does the VREF source supply the minimal current required by the system (memories + processor)?
6. If a resistor divider network is used to generate VREF, are both resistors the same value and 1% tolerance?

Routing

Suggest routing order within the DDR2 interface: 1) Data, 2) Address/Command, 3) Control, 4) Clocks, and 5) Power This order allows the clocks to be tuned easily to the other signal groups. It also assumes an open critical layer on which clocks are freely routed.

Global items—Do not route any DDR2 signals overs splits or voids. Traces routed near the edge of a reference plane should maintain at least 30–40 mil gap to the edge of the reference plane.
Allow no more than 1/2 of a trace width to be routed over via antipad.

When routing the data lanes, route the outermost (that is, longest lane first) because this determines the amount of trace length to add on the inner data lanes.

Are the clock pair assignments optimized to allow break-out of all pairs on a single critical layer?

The DDR2 data bus consists of 9 data byte lanes (assuming ECC is used). All signals within a given byte lane should be routed on the same critical layer with the same via count.
Note: Some product implementations may only implement a 32-bit wide interface.

• Byte Lane 0—MDQ(7:0), MDM(0), MDQS(0), MDQS(0)
• Byte Lane 1—MDQ(15:8), MDM(1), MDQS(1), MDQS(1)
• Byte Lane 2—MDQ(23:16), MDM(2), MDQS(2), MDQS(2)
• Byte Lane 3—MDQ(31:24), MDM(3), MDQS(3), MDQS(3)
• Byte Lane 4—MDQ(39:32), MDM(4), MDQS(4), MDQS(4)
• Byte Lane 5—MDQ(47:40), MDM(5), MDQS(5), MDQS(5)
• Byte Lane 6—MDQ(55:48), MDM(6), MDQS(6), MDQS(6)
• Byte Lane 7—MDQ(63:56), MDM(7), MDQS(7), MDQS(7)
• Byte Lane 8—MECC(7:0), MDM(8), MDQS(8), MDQS(8)

To facilitate fan-out of the DDR2 data lanes (if needed), alternate adjacent data lanes onto different critical layers?

Note: If the device supports ECC, Freescale highly recommends that the user implement ECC on
the initial hardware prototypes.

DDR2 data group—Impedance range and spacing

• Single-ended target Impedance = 50–60 Ω range (MDQ, MDM)
• Differential target impedance = 100–120 Ω range (MDQS, MDQS) Note: Some product implementations may support only the single-ended version of the strobe.
• Referenced to a solid ground plane, thereby providing a low-impedance path for return currents.
• Trace space to other non-DDR2 data groups = 25 mil.
• Trace space requirements within the DDR2 data group = 10 mils (reducing to 7 mils inside the DIMM area). Note: Based on a trace width of 5 mil.

Across all DDR2 data lanes, are all the data lanes matched to within 0.5 inch?

Is each data lane properly trace matched to within 20 mils of its respective differential data strobe? (Assumes highest frequency operation.)

When adding trace lengths to any of the DDR2 signal groups, ensure that there is at least 25 mils between serpentine loops that are in parallel.

MDQS/MDQS differential strobe routing
Note: Some product implementations may support only the single-ended version of the strobe.

• Match all segment lengths between differential pairs along the entire length of the pair. Trace match the MDQS/ MDQS pair to be within 10 mils.
• Maintain constant line impedance along the routing path by maintaining the required line width and trace separation for the given stackup.
• Avoid routing differential pairs adjacent to noisy signal lines or high speed switching devices such as clock chips.
• Differential Impedance = 100–120 (50–60 Ω single ended with proper spacing)
• Do not divide the two halves of the diff pair between layers. Route MDQS/MDQS pair on the samecritical layer as its associated data lane.

DDR2 address/command group—Impedance range and spacing

• Single-Ended Target Impedance = 50–60 Ω range
• Match all traces to within 100 mils
• Referenced to a contiguous 1.8-V power reference (DIMM implementations currently do this)
• Referenced to a contiguous 1.8-V power reference or ground plane (discrete implementations)
• Trace space to other non-DDR2 address/cmd signals = 25 mil.
• Trace space requirements within the DDR2 address/cmd group = 10 mils (reducing to 7 mils inside the DIMM area). Note: Based on a trace width of 5 mil.

DDR2 control group—Impedance range and spacing

• Single-Ended Target Impedance = 50–60 Ω range
• Match all traces to within 100 mils
• Referenced to a contiguous 1.8-V power reference (DIMM implementations currently do this)
• Referenced to a contiguous 1.8-V power reference or ground plane (discrete implementations)
• Trace space to other non-DDR2 control groups = 25 mil.
• Trace space requirements within the DDR2 control group = 10 mils (reducing to 7 mils inside the DIMM area). Note: Based on a trace width of 5 mil.

Are the DDR2 signal groups tuned to the clock reference? Because this is loading and topology dependent, the variance around the clock should be determined by simulation. Secondly, in multi-bank systems, are the address and command signals loaded more heavily than the control signals (CS, ODT, CKE)?
Specifically:

• Are the setup/hold optimized for the addr/cmd group?
• Are the steup/hold optimized for the control group (CS, ODT, CKE)?
• Is the write data delay window met (tDQSS)? This is the relationship between the data strobes and clocks as specified by the JEDEC DDR2 specification.

Are the DDR2 differential clocks properly routed?

• Match all segment lengths between differential pairs along the entire length of the pair. Trace match the MCK/ MCK pair to be within 10 mils.
• Maintain constant line impedance along the routing path by maintaining the required line width and trace separation for the given stackup.
• Avoid routing differential pairs adjacent to noisy signals lines or high speed switching devices such as clock chips.
• Differential Impedance = 100–120 (50–60 Ω single ended with proper spacing)
• Do not divide the two halves of the diff pair between layers. Route MCK/MCK pair on the same critical layer.

Are all clock pairs routed on the same critical layer (one referenced to a solid ground plane)?

Are all clock pairs properly trace matched to within 25 mils of each other?

The space from one differential pair to any other trace (this includes other differential pairs) should be at least 25 mils.

If unbuffered DIMM modules are used, are all three required clock pairs per DIMM slot connected?

If the optional 0-Ω resistors are used (as noted in item 10), use ground stitching vias near the resistors.

MODT/MDIC Related Items

Are the MODT signals connected correctly?

• MODT(0), MCS(0), MCKE(0) should all go to the same physical memory bank.
• MODT(1), MCS(1), MCKE(1) should all go to the same physical memory bank.
• MODT(2), MCS(2), MCKE(2) should all go to the same physical memory bank.
• MODT(3), MCS(3), MCKE(3) should all go to the same physical memory bank.

Is MDIC0 connected to ground via an 18.2-Ω precision 1% resistor? Is MDIC1 connected to DDR
power via an 18.2-Ω precision 1% resistor?

Ethernet Component Layout Guidelines

These sections provide recommendations for performing printed circuit board layouts. Good layout practices are essential to meet IEEE PHY conformance specifications and EMI regulatory requirements.

Critical signal traces should be kept as short as possible to decrease the likelihood of being affected by high frequency noise from other signals, including noise carried on power and ground planes. Keeping the traces as short as possible can also reduce capacitive loading.

Since the transmission line medium extends onto the printed circuit board, special attention must be paid to layout and routing of the differential signal pairs. Designing for 1000 BASE-T Gigabit operation is very similar to designing for 10 and 100Mbps.

Guidelines for Component Placement

Component placement can affect signal quality, emissions, and component operating temperature This section provides guidelines for component placement.
Careful component placement can:

• Decrease potential problems directly related to electromagnetic interference (EMI), which could cause failure to meet applicable government test specifications.
• Simplify the task of routing traces. To some extent, component orientation will affect the complexity of trace routing. The overall objective is to minimize turns and crossovers between traces.
• Minimizing the amount of space needed for the Ethernet LAN interface is important
• because other interfaces will compete for physical space on a motherboard near the
• connector. The Ethernet LAN circuits need to be as close as possible to the connector.

General Placement Distances for 1000 BASE-T Designs

• Picture below shows some basic placement distance guidelines. The figure shows two differential pairs, but can be generalized for a Gigabit system with four analog pairs.
• The ideal placement for the Ethernet silicon would be approximately one inch behind the magnetics module.
• While it is generally a good idea to minimize lengths and distances, this figure also
• illustrates the need to keep the LAN silicon away from the edge of the board and the magnetics module for best EMI performance.

The following figures illustrate a reference layout for discrete and integrated magnetics.

Crystals and Oscillators

Clock sources should not be placed near I/O ports or board edges. Radiation from these devices may be coupled into the I/O ports and radiate beyond the system chassis. Crystals should also be kept away from the Ethernet magnetics module to prevent interference.

Crystal layout considerations

Failure to follow these guidelines could result in the 25 MHz clock failing to start. When designing the layout for the crystal circuit, the following rules must be used:

• Place load capacitors as close as possible (within design-for-manufacturabilityrules) to the crystal solder pads. They should be no more than 90 mils away fromcrystal pads.
• The two load capacitors, crystal component, the Ethernet controller device, and thecrystal circuit traces must all be located on the same side of the circuit board(maximum of one via-to-ground load capacitor on each Xtal trace).
• Use 27 pF (5% tolerance) 0402 load capacitors.
• Place load capacitor solder pad directly in line with circuit trace (see picture above,point A).
• Place a 30-ohm (5% tolerance) 0402 series resistor on Xtal2 (see picture above, pointC). The location of the resistor along the Xtal2 trace is flexible, as long as it isbetween the load capacitor and the controller.
• Use 50-ohm impedance single-ended microstrip traces for the crystal circuit.
• Route traces so that electro-magnetic fields from Xtal2 do not couple onto Xtal1.
• No differential traces.
• Route Xtal1 and Xtal2 traces to nearest inside corners of crystal pad (see picture below, point B).
• Ensure that the traces from Xtal1 and Xtal2 are symmetrically routed and that their lengths are matched.
• The total trace length of Xtal1 or Xtal2 should be less than 750 mils.

Board Stack Up Recommendations

Printed circuit boards for these designs typically have six, eight, or more layers.
Although, the 82575 does not dictate the stackup, here is an example of a typical six layer board stackup:

• Layer 1 is a signal layer. It can contain the differential analog pairs from the Ethernet device to the magnetics module, or to an optical transceiver.
• Layer 2 is a signal ground layer. Chassis ground may also be fabricated in Layer 2 under the connector side of the magnetics module.
• Layer 3 is used for power planes.
• Layer 4 is a signal layer.
• Layer 5 is an additional ground layer.
• Layer 6 is a signal layer. For 1000 BASE-T (copper) Gigabit designs, it is common toroute two of the differential pairs (per port) on this layer.

This board stack up configuration can be adjusted to conform to your company's design
rules.

Gigabit Ethernet Controller Design --> General Design Considerations for Ethernet Controllers

Follow good engineering practices with respect to unused inputs by terminating them with pull-up or pull-down resistors, unless the datasheet, design guide or reference schematic indicates otherwise. Do not attach pull-up or pull-down resistors to any balls identified as No Connect. These devices may have special test modes that could be entered unintentionally.

Clock Source

All designs require a 25 MHz clock source. The Gigabit Ethernet Controller uses the 25 MHz source to generate clocks up to 125 MHz and 1.25 GHz for the PHY circuits, and 1.25 GHz for the SERDES. For optimum results with lowest cost, connect a 25 MHz parallel resonant crystal and appropriate load capacitors at the XTAL1 and XTAL2 leads. The frequency tolerance of the timing device should be 30 ppm or better.

Magnetics for 1000 BASE-T

Magnetics for the Gigabit Ethernet can be either integrated or discrete. The magnetics module has a critical effect on overall IEEE and emissions conformance. The device should meet the performance required for a design with reasonable margin to allow for manufacturing variation. Occasionally, components that meet basic specifications may cause the system to fail IEEE testing because of interactions with other components or the printed circuit board itself. Carefully qualifying new magnetics modules prevents this problem.

When using discrete magnetics it is necessary to use Bob Smith termination: Use four
75 Ω resistors for cable-side center taps and unused pins. This method terminates pairto- pair common mode impedance of the CAT5 cable.

Use an EFT capacitor attached to the termination plane. Suggested values are 1500 pF/
2KV or 1000 pF/3KV. A minimum of 50-mil spacing from capacitor to traces and
components should be maintained.

Magnetics Module Qualification Steps

The steps involved in magnetics module qualification are similar to those for crystal
qualification:

1. Verify that the vendor’s published specifications in the component datasheet meet or exceed the required IEEE specifications.
2. Independently measure the component’s electrical parameters on the test bench, checking samples from multiple lots. Check that the measured behavior is consistent from sample to sample and that measurements meet the published specifications.
3. Perform physical layer conformance testing and EMC (FCC and EN) testing in real
4. systems. Vary temperature and voltage while performing system level tests.

Modules for 1000 BASE-T Ethernet

Magnetics modules for 1000 BASE-T Ethernet are similar to those designed solely for
10/100 Mbps, except that there are four differential signal pairs instead of two. Use the
following guidelines to verify specific electrical parameters:

1. Verify that the rated return loss is 19 dB or greater from 2 MHz through 40 MHz for 100/1000 BASE-TX.
2. Verify that the rated return loss is 12 dB or greater at 80 MHz for 100 BASE-TX (the specification requires greater than or equal to 10 dB).
3. Verify that the rated return loss is 10 dB or greater at 100 MHz for 1000 BASE-TX (the specification requires greater than or equal to 8 dB).
4. Verify that the insertion loss is less than 1.0 dB at 100 kHz through 80 MHz for 100 BASE-TX.
5. Verify that the insertion loss is less than 1.4 dB at 100 kHz through 100 MHz for 1000 BASE-T.
6. Verify at least 30 dB of crosstalk isolation between adjacent channels (through 150 MHz).
7. Verify high voltage isolation to 15000 Vrms. (Does not apply to discrete magnetics.)
8. Transmitter OCL should be greater than or equal to 350 μH with 8 mA DC bias.

Gigabit Ethernet Controller Design Consideration --> Ethernet Magnetic Layout Considerations

The Ethernet magnetic layout considerations are dependent on the external PHY. Please refer to the preferred external PHY Ethernet magnetic layout guide for the detailed requirements.


The following are some general Gigabit Ethernet layout considerations for the differential signals of the Gigabit Ethernet PHY, the Ethernet magnetic and the RJ-45 connector. All trace routes from 10/100/1000M magnetic, RJ-45, and Gigabit Ethernet PHY should be as short as possible. It is an appropriate policy to have the same length for all differential pair signal traces. General speaking, reducing signal crosstalk, providing a solid ground plane, and decreasing parallel route should be considered.

1. The crystal/oscillator clock source and the switching noises from digital signals should be kept away from the MDI0±, MDI1±, MDI2±, and MDI3± differential pairs. Moreover, the crystal/oscillator may be sensitive to wander capacitances and noise from other signals; it is better to deploy the crystal far away from I/O ports, high frequency signal traces, magnetic, board edges, and so on.
2. The Ethernet magnetic should be placed as close to the RJ-45 connector as possible.
3. The Gigabit Ethernet PHY should be placed as close as possible to the magnetic. If there are some limitations on the PCB layout, the trace length from the Gigabit Ethernet PHY to the magnetic should not be longer than 5 inches.
4. The MDI0±, MDI1±, MDI2±, and MDI3± differential pairs should be routed as close as possible. The trace spacing D1 between MDI0+ and MDI0- (or between MDI1+ and MDI1-, MDI2+ and MDI2-, MDI3+ and MDI3-) pair should be in 8 ~ 10 mils. The trace width should be adjusted accordingly to yield the required trace impedance.
5. The spacing D2 should be larger than 200 mils. If the PCB layout is really difficult to meet this requirement, the D2 spacing should be as larger as possible.
6. Route the MDI0±, MDI1±, MDI2±, and MDI3± differential pairs as straight as possible and keep them in parallel for differential pairs.
7. Keep the trace length difference between MDI0+ and MDI0- (or between MDI1+ and MDI1-, MDI2+ and MDI2-, MDI3+ and MDI3-) pair within 700 mils.
8. The termination resistors 49.9Ω and capacitors of the MDI0±, MDI1±, MDI2± and MDI3± differential pairs should be placed as close to the magnetic as possible and the trace should be shorter than 400 mils.
9. Route the MDI0±, MDI1±, MDI2±, and MDI3± differential pairs running symmetric, equal length and close whenever possible.
10. Avoid using vias on the traces of the MDI0±, MDI1±, MDI2±, and MDI3± differential pairs. If the PCB layout really needs to use vias on the differential pairs, please match the vias to keep the differential pairs balanced.
11. The power plane and digital ground plane should not be placed under the magnetic and RJ-45 connector.
12. Avoid routing the signal trace with right angle, instead, the signal trace should be routed with multiple 45˚ angles.

Gigabit Ethernet Controller Design Guidelines --> Power and Ground Planes Considerations

The RJ-45 chassis ground and the digital ground should be isolated through a 1M Ohm resistor and a 0.1uF decoupling capacitor. And the gap between the chassis ground and digital ground must be wider than 60 mils.



All the digital and analog power planes for different voltage supplies should be isolated.




Note:

1. The above figures are the Digital Power (VDDxx) and Analog Power (AVDDxx) planes diagram of an illustrative LAN board design. For exact layout pattern, ASIX Electronics provides some demo boards and the layout PCB files and Gerber files for customer reference.
2. VDDK: Digital Core Power 2.5V
3. VDD2: Digital I/O Power 2.5V
4. AVDDK: Analog Core Power 2.5V

Provide a power plane right underneath the ASIX Ethernet controller such that the VCC pins can be contacted to the power plane without going through thin traces.


All power pins should be implemented with a decoupling capacitor, and the decoupling capacitor should be as close to the respective power pin of ASIX Ethernet controller as possible.