Sunday, July 26, 2009

Ethernet Component Layout Guidelines

These sections provide recommendations for performing printed circuit board layouts. Good layout practices are essential to meet IEEE PHY conformance specifications and EMI regulatory requirements.

Critical signal traces should be kept as short as possible to decrease the likelihood of being affected by high frequency noise from other signals, including noise carried on power and ground planes. Keeping the traces as short as possible can also reduce capacitive loading.

Since the transmission line medium extends onto the printed circuit board, special attention must be paid to layout and routing of the differential signal pairs. Designing for 1000 BASE-T Gigabit operation is very similar to designing for 10 and 100Mbps.

Guidelines for Component Placement

Component placement can affect signal quality, emissions, and component operating temperature This section provides guidelines for component placement.
Careful component placement can:
  • Decrease potential problems directly related to electromagnetic interference (EMI), which could cause failure to meet applicable government test specifications.
  • Simplify the task of routing traces. To some extent, component orientation will affect the complexity of trace routing. The overall objective is to minimize turns and crossovers between traces.
  • Minimizing the amount of space needed for the Ethernet LAN interface is important
  • because other interfaces will compete for physical space on a motherboard near the
  • connector. The Ethernet LAN circuits need to be as close as possible to the connector.

General Placement Distances for 1000 BASE-T Designs
  • Picture below shows some basic placement distance guidelines. The figure shows two differential pairs, but can be generalized for a Gigabit system with four analog pairs.
  • The ideal placement for the Ethernet silicon would be approximately one inch behind the magnetics module.
  • While it is generally a good idea to minimize lengths and distances, this figure also
  • illustrates the need to keep the LAN silicon away from the edge of the board and the magnetics module for best EMI performance.
The following figures illustrate a reference layout for discrete and integrated magnetics.

Crystals and Oscillators

Clock sources should not be placed near I/O ports or board edges. Radiation from these devices may be coupled into the I/O ports and radiate beyond the system chassis. Crystals should also be kept away from the Ethernet magnetics module to prevent interference.

Crystal layout considerations

Failure to follow these guidelines could result in the 25 MHz clock failing to start. When designing the layout for the crystal circuit, the following rules must be used:


  • Place load capacitors as close as possible (within design-for-manufacturabilityrules) to the crystal solder pads. They should be no more than 90 mils away fromcrystal pads.
  • The two load capacitors, crystal component, the Ethernet controller device, and thecrystal circuit traces must all be located on the same side of the circuit board(maximum of one via-to-ground load capacitor on each Xtal trace).
  • Use 27 pF (5% tolerance) 0402 load capacitors.
  • Place load capacitor solder pad directly in line with circuit trace (see picture above,point A).
  • Place a 30-ohm (5% tolerance) 0402 series resistor on Xtal2 (see picture above, pointC). The location of the resistor along the Xtal2 trace is flexible, as long as it isbetween the load capacitor and the controller.
  • Use 50-ohm impedance single-ended microstrip traces for the crystal circuit.
  • Route traces so that electro-magnetic fields from Xtal2 do not couple onto Xtal1.
  • No differential traces.
  • Route Xtal1 and Xtal2 traces to nearest inside corners of crystal pad (see picture below, point B).
  • Ensure that the traces from Xtal1 and Xtal2 are symmetrically routed and that their lengths are matched.
  • The total trace length of Xtal1 or Xtal2 should be less than 750 mils.

Board Stack Up Recommendations

Printed circuit boards for these designs typically have six, eight, or more layers.
Although, the 82575 does not dictate the stackup, here is an example of a typical six layer board stackup:
  • Layer 1 is a signal layer. It can contain the differential analog pairs from the Ethernet device to the magnetics module, or to an optical transceiver.
  • Layer 2 is a signal ground layer. Chassis ground may also be fabricated in Layer 2 under the connector side of the magnetics module.
  • Layer 3 is used for power planes.
  • Layer 4 is a signal layer.
  • Layer 5 is an additional ground layer.
  • Layer 6 is a signal layer. For 1000 BASE-T (copper) Gigabit designs, it is common toroute two of the differential pairs (per port) on this layer.
This board stack up configuration can be adjusted to conform to your company's design
rules.

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