Touch Sensor PCB and Layout Guidelines Part 1

Introduction

This note provides guidelines for the construction and the layout of different types of printed circuit boards (PCBs) for the implementation of the Touch Sensor Controller (TSC) capacitive sensors on substrate materials such as FR4, flexible PCBs, or ITO panels. Various substrate materials are available for different PCB design construction. Among the substrate materials currently available on the market, the FR4 is the most common. FR4 is a glass fiber epoxy laminate and PCBs can have one or several layers. Given a limited size of the touch module, the one-layer PCB implementation is not always possible, whereas the fourlayer and the two-layer PCB are more common. For applications requiring a very compact form factor, a flexible PCB can be used. The capacitive touch module on top of the display unit requires a transparent sensor electrode and traces which can be implemented using an Indium Tin Oxide (ITO) layer on a glass/plastic panel.

PCB Design Tips

The Noise Influence by Other Chips

In the touch module, it is recommended that only the Controller be mounted without any other chips because other chips can cause noise signals when controlling components such as LCD or Buzzer, etc.

Cross Coupling Capacitance

Noise signals can be generated between sensor input lines. If sensor lines are both very close to each other and placed in parallel, they can become noise sources to one another. In order to avoid this, it is recommended to design sensor input lines as shown in Figure 2. Enlarge line spacing and make parallel portions as short as possible.

Disposition of Data Lines and Sensor Input Lines

Figure 3 on the following page shows a problem caused by overlapping sensor input lines with data lines. For example, the capacitance generated by power lines with characteristics of consistent voltage output will not deeply affect sensor input lines. However, the capacitance generated by data lines fluctuating high and low voltage output will make sensor input lines unstable. Thus, the data lines in the front panel application should be placed closer to the connector in order to avoid undesirable influence on sensor input lines. Another important aspect in layout design is that sensor input lines should be placed on the opposite side of data output lines. Finally, since overlapping data lines with sensor touch pads will be worse than overlapping data lines with sensor input lines, it is recommended that sensor pads should be apart from data lines.
Several Controller Sensor Line Noise

If two Controller chips are mounted on the same PCB, they can be noise sources to each other. Therefore, in applications that are using two Controller chips, you need to design the touch pad area as shown in Figure 4.

LCD Control Signal Noise Issue

If the PCB, which includes LCD control lines, is located near a touch PCB, it could be a noise source even if it is not on the same PCB. Therefore, you need to design the PCB like Figure 5, which is less affected by LCD control signals. Any kind of pulse-type signals should be as far from the Controller as possible.



Charge Sharing

The sensitivity of the Controller will be decreased if the GND pattern is located close to the sensor input pads and lines because an electrical field generated by GND patterns will attenuate the strength of the capacitance generated by finger touch. This will decrease the sensitivity of the sensor input as shown in (a) of Figure 6 on the next page. Although the GND pattern is used to reduce the interference of the lines, make sure to keep the GND pattern a distance from the sensor input pads.



Mismatch in Each Sensor Input

For a normal AIC function, each sensor input capacitance of the system should be within 6pF.

Large Sensor Input Pad

If a touch pad is larger than 10 x 10mm, it will become very sensitive to external environmental change. As a result, input impedance during no-touch could be unstable. In order to avoid this situation, it is recommended to use a pad layout as shown in example (b) of Figure 7, which is exactly the same pad size as shown in example (a), but it eliminates the problem by reducing real surface area.



Touch Sensor PCB and Layout Guidelines Part 2

General Routing Techniques with Emphasis on PI6C10X Clocks -- > Part 3

Clock traces can easily become antennas. 100 MHz clock running through a narrow trace can radiate EMI and affect the FM radio sitting next to the system. As is evident, 100MHz is right at the middle of the FM radio spectrum. The way to further decrease the EMI radiation is to guard against improper loading and mismatches. To practically eliminate this problem, the source impedance of the clock driver should be matched in impedance to the load and the circuit trace. Most often a series termination is placed as close as possible to the source.


Theoretically the output impedance of the clock driver plus the value of the termination should be equal to the impedance of the PCB transmission line. If there is an impedance mismatch between the low-impedance source and high-impedance load, voltage reflection can occur from the load. This will result in overshoot and undershoot of the signal. The output impedance of the clock driver ranges from 20 to 30 ohms. To match this with a 50-ohms transmission line, a 30 to 20 ohms damping resistor should be chosen. The draw back is that the termination resistor reduces the amount of current and in effect reduces the clock waveform rise and fall time.
It is very important to choose a proper value of damping resistor since any excessive voltage drop may increase the clock Jitter.

To reduce ground bounce that causes Jitter, a full ground plane under the device is necessary. All bypass capacitors are connected to this ground plane. Each ground pin should be connected to the ground plane individually. Daisy chain grounding should not be practiced since it allows sharing the ground path. No high frequency signal should be routed under the device since high frequency clocks tend to capacitive and inductively couple into the device and cause Jitter in the PLL. Picture shown below, illustrate the recommended PCB layout for the power supply bypassing the clock generator and the CK100 clock buffer, respectively. This method dramatically reduces the noise that may enter the PLL and cause Jitter. The value of the resistor should not be too high to stop the device from proper functioning.

The PI6C18X Clock Buffer

The PI6C18X is a buffer device that removes large switching current from the actual clock generation device. The PI6C18X, however, introduces a delay of up to 5ns. The Intel chipset and new chipsets resolve this problem by providing the clock to the PI6C18X. The chipset can read the exact amount of the delay and can compensate for this delay. In effect the chipset adjusts the SDRAM timing to optimize the relationship between CPU and SDRAM timing.

EMI Reducing Capacitors

If the amount of EMI is still very high in a system, it is possible to alleviate this condition even further by using a special type of capacitor. The EMI reducing capacitor is mainly used on the output clocks to round the falling and rising edges of the clock and hence reduce the radiation from sharp edges. The EMI reduction capacitors usually range from 4pF to 25pF. They are placed very close to terminating resistors between the resistor and the load. No connection should be made to clocks that are not used. No termination is recommended for unused clock pins. Since these devices are CMOS, they draw large impulse current. If the power supply bypassing is not adequate, the noise as the result of these transitions may enter the device analog section and increase the jitter. Where possible, disable unused clock outputs.

Ground Plane Localization

The entire board must have a separate ground plane, however, it is strongly recommended to localize the ground plane for the clock generator. This localized ground plane is then connected to the main board ground plane through Vias and device pins.

Other Routing Issues

The clock must be placed near the center of the board and near a chassis ground. Clock traces should not intersect each other. All clock signals must be hand routed before any other signals.

More tips on routing and connections: Do not use 90 degree angles when routing clock traces. If possible, always use curvy traces. Do not route any other signals below the clock generator. A solid ground plane must be placed on the layer adjacent to a clock trace routing layer. Vias should be avoided on clock signals. Vias cause reflection by changing trace impedance. Vias should not cause discontinuities either. For low skew, signal traces must be of matched length and loading, and, if possible, identical. If certain signals are supposed to have certain skews with each other, their trace length must be equal. Do not use T connections. For minimum
skew, use one load per clock output.



Board Layout for Reducing EMI and Preserving Signal Integrity

It is recommended that you calculate the capacitive loading and compensate with a series damping resistor and/or end termination. Do not locate clock signals near I/O areas. To minimize reflections and ringing keep trace impedance balanced and short. It is highly recommended that you rout clock traces on one routing plane only. At all times this layer must be adjacent to a solid image plane. It is better to create localized ground and VCC planes on the top layer of the PCB. The localized ground plane should be beneath the chip and the VCC plane surrounds the chip. These planes provide a path for RF currents to return to ground.

Most Important EMC Design Guidelines

Minimize the loop areas associated with high-frequency power and signal currents.

This simple rule is on nearly everybody's list of EMC guidelines, but it often gets ignored or compromised in favor of other guidelines. Often the board designer doesn't even know where the signal currents flow. Digital circuit designers like to think of signals in terms of their voltage. Signal integrity and EMC engineers must think of signals in terms of their current.

There are two things that every good circuit designer should know about signal currents.

1. Signal currents always return to their source (i.e. current paths are always loops)
2. Signal currents take the path(s) of least impedance.

At megahertz frequencies and higher, signal current paths are relatively easy to identify. This is because the path of least impedance at high frequencies is generally the path of least inductance, which is generally the path that minimizes the loop area. Currents return as close as possible to the path of the outgoing current. At low frequencies (generally kHz frequencies and below), the path of least impedance tends to be the path(s) of least resistance. Low frequency currents are more difficult to trace, since they will spread out. Significant current return paths may be relatively distant from the outgoing current path.

Don't Split, Gap or Cut the Signal Return Plane

Sure, there are some situations where a well-placed gap in the return plane is called for. However, these are relatively rare and always involve a need to control the flow of low-frequency currents. The safest rule-of-thumb is to provide one solid plane for returning all signal currents. In situations where you expect that a particular low-frequency signal is susceptible or is capable of interfering with the circuitry on your board, use a trace on a separate layer to return that current to its source. In general, never split, gap or cut your board's signal return plane. If you are convinced that a gap is necessary to prevent a low-frequency coupling problem, seek advice from an expert. Don't rely on design guidelines or application notes and don't try to implement a scheme that "worked" in someone else's "similar" design.



Don't Locate High-Speed Circuitry between Connectors

Among board designs that we have reviewed or evaluated in our lab, this is one of the most common problems we've encountered. Many times simple board designs that should have had no trouble at all meeting EMC requirements at no additional cost or effort, wind up being heavily shielded and filtered because they violated this simple rule.

Why is the location of connectors so important? At frequencies below a few hundred megahertz, wavelengths are on the order of a meter or longer. Any possible antennas on the printed circuit board itself tend to be electrically small and therefore inefficient. However, cables or other devices connected to a board can serve as relatively efficient antennas.

Signal currents flowing on traces and returning through solid planes result in small voltage differences between any two points on the plane. These voltage differences are generally proportional to the current flowing in the plane. When all connectors are placed along one edge of a board, the voltage between them tends to be negligible. However, high-speed circuitry located between connectors can easily develop potential differences of a few millivolts or greater between the connectors. These voltages can drive currents onto attached cables causing a product to exceed radiated emissions requirements.

Control Signal Transition Times

A board operating with a clock speed of 100 MHz should never fail to meet a radiated emissions requirement at 2 GHz. A well-formed digital signal will have a significant amount of power in the lower harmonic frequencies, but not so much power in the upper harmonics. Power in the upper harmonic frequencies is best controlled by controlling the transition times in digital signals. Longer transition times are preferred for EMC. Excessively long transition times can cause signal integrity and thermal problems. An engineering compromise must be reached between these competing requirements. A transition time that is approximately 20% of a bit period results in a reasonably good-looking waveform, while minimizing problems due to crosstalk and radiated emissions. Depending on the application, transitions times may need to be more or less than 20% of the bit period, however transitions times should not be left to chance.

There are three common methods for controlling rise and fall times in digital logic.

1. Use a logic family that is only as fast as the application requires.
2. Put a resistor or a ferrite in series with a device's output.
3. Put a capacitor in parallel with a device's output.

The first choice is often the easiest and most effective option. However, the use of a resistor or ferrite gives the designer more control and is less affected by changes that occur in logic families over time. Capacitors can actually increase the amount of high-frequency current drawn by the source device and in most cases are not an appropriate choice.

Note that it is never a good idea to try to slow down or filter a single-ended signal by impeding the flow of current in the return path. For example, one should never intentionally route a low-speed trace over a gap in a return plane in an attempt to filter out the high-frequency noise. After reviewing the first two design guidelines, this should be obvious. Nevertheless, boards employing this flawed design strategy occasionally show up in our lab.

SIGNAL INTEGRITY

In the realm of high-speed digital design, signal integrity has become a critical issue, and is posing increasing challenges to the design engineers. Many signal integrity problems are electromagnetic phenomena in nature and hence related to the EMI/EMC discussions in the previous sections of this blog. We will discuss what the typical signal integrity problems are, where they come from, why it is important to understand them and how we can analyze and solve these issues. Several software tools available at present for signal integrity analysis and current trends in this area will also be introduced.

The term Signal Integrity (SI) addresses two concerns in the electrical design aspects – the timing and the quality of the signal. Does the signal reach its destination when it is supposed to? And also, when it gets there, is it in good condition? The goal of signal integrity analysis is to ensure reliable high-speed data transmission. In a digital system, a signal is transmitted from one component to another in the form of logic 1 or 0, which is actually at certain reference voltage levels. At the input gate of a receiver, voltage above the reference value Vih is considered as logic high, while voltage below the reference value Vil is considered as logic low. Picture - 1 shows the ideal voltage waveform in the perfect logic world, whereas Picture - 2 shows how signal will look like in a real system. More complex data, composed of a string of
bit 1 and 0s, are actually continuous voltage waveforms. The receiving component needs to sample the waveform in order to obtain the binary encoded information. The data sampling process is usually triggered by the rising edge or the falling edge of a clock signal as shown in the Picture 3. It is clear from the diagram that the data must arrive at the receiving gate on time and settle down to a non-ambiguous logic state when the receiving component starts to latch in. Any delay of the data or distortion of the data waveform will result in a failure of the data transmission. Imagine if the signal waveform in Picture - 2 exhibits excessive ringing into the logic gray zone while the sampling occurs, then the logic level cannot be reliably detected.

Picture 1



Picture 2

Picture 3

Typical SI Problems

“Timing” is everything in a high-speed system. Signal timing depends on the delay caused by the physical length that the signal must propagate. It also depends on the shape of the waveform when the threshold is reached. Signal waveform distortions can be caused by different mechanisms. But there are three mostly concerned noise problems:

--> Reflection Noise
Due to impedance mismatch, stubs, vias and other interconnect discontinuities.

--> Crosstalk Noise
Due to electromagnetic coupling between signal traces and vias.

--> Power/Ground Noise
Due to parasitics of the power/ground delivery system during drivers’ simultaneous switching output (SSO). It is sometimes also called Ground Bounce, Delta-I Noise or Simultaneous Switching Noise (SSN).

Besides these three kinds of SI problems, there are other Electromagnetic Compatibility or Electromagnetic Interference (EMC/EMI) problems that may contribute to the signal waveform distortions. When SI problems happen and the system noise margin requirements are not satisfied – the input to a switching receiver makes an inflection below Vih minimum or above Vil maximum; the input to a quiet receiver rises above Vil maximum or falls below Vih minimum; power/ground voltage fluctuations disturb the data in the latch, then logic error, data drop, false switching, or even system failure may occur. These types of noise faults are extremely difficult to diagnose and solve after the system is built or prototyped. Understanding and solving these problems before they occur will eliminate having to deal with them further into the project cycle, and will in turn cut down the development cycle and reduce the cost. In the later part of this chapter, we will have further investigations on the physical behavior of these noise phenomena, their causes, their electrical models for analysis and simulation, and the ways to avoid them.

Where SI Problems Happen

Since the signals travel through all kinds of interconnections inside a system, any electrical impact happening at the source end, along the path, or at the receiving end, will have great effects on the signal timing and quality. In a typical digital system environment, signals originating from the off-chip drivers on the die (the chip) go through c4 or wire-bond connections to the chip package. The chip package could be single chip carrier or multi-chip module (MCM). Through the solder bumps of the chip package, signals go to the Printed Circuit Board (PCB) level. At this level, typical packaging structures include daughter card, motherboard or backplane. Then signals continue to go to another system component, such as an ASIC (Application Specific Integrated Circuit) chip, a memory module or a termination block. The chip
packages, printed circuit boards, as well as the cables and connecters, form the so-called ifferent levels of electronic packaging systems, as illustrated in below. In each level of the packaging structure, there are typical interconnects, such as metal traces, vias, and power/ground planes, which form electrical paths to conduct the signals. It is the packaging interconnection that ultimately influences the signal integrity of a system.


SI In Electronic Packaging

Technology trends toward higher speed and higher density devices have pushed the package performance to its limits. The clock rate of present personal computers is approaching gigahertz range. As signal risetime becomes less than 200ps, the significant frequency content of digital signals extends up to at least 10 GHz. This necessitates the fabrication of interconnects and packages to be capable of supporting very fast varying and broadband signals without degrading signal integrity to unacceptable levels. While the chip design and fabrication technology have undergone a tremendous evolution: gate lengths, having scaled from 50 μm in the 1960s to 0.18 μm today, are projected to reach 0.1 μm in the next few years; on-chip clock frequency is doubling every 18 months; and the intrinsic delay of the gate is decreasing exponentially with time to a few tens of pico-seconds. However, the package design has lagged considerably. With current technology, the package interconnection delay dominates the system timing budget and becomes the bottleneck of the high-speed system design. It is generally accepted today that package performance is one of the major limiting factors of the overall system performance.

Advances in high performance sub-micron microprocessors, the arrival of gigabit networks, and the need for broadband Internet access, necessitate the development of high performance packaging structures for reliable high-speed data transmission inside every electronics system. Signal integrity is one of the most important factors to be considered when designing these packages (chip carriers and PCBs) and integrating these packages together.

Crosstalk

Crosstalk is yet another major concern for PCB designers. Figure 8a shows the cross section of a PCB indicating three parallel traces and their associated electromagnetic (EM) fields. When the spacing between the traces is too narrow, the EM fields of the traces will interact and the signals on the traces become corrupted as shown below. This is called crosstalk.


Crosstalk can be corrected by increasing the spacing between the spacing between tracks. However, PCB designers are under constant pressure to shrink their layouts and hence reduce the gap between tracks. Also, there are times when a designer has no alternative but to wear some amount of crosstalk in their design. Clearly, PCB designers need a strategy of managing crosstalk.



Many ‘rules of thumb’ have been published over the years about what is an acceptable spacing between conductors. A common rule is the 3W rule where the spacing between traces must be at least three times the width of the trace.

However the reality is that ‘acceptable’ spacing between conductors depends upon the application, the environment and the design margins. The spacing between traces changes from one situation to another and must be calculated for each. Furthermore, there are times when crosstalk can’t be avoided and the impact of crosstalk must be calculated. In these situations there is no substitution for a computer simulation.

A good example of these issues is in high-speed, high-density connectors. Here the PCB designer may know that there is some amount of crosstalk between the conductors and he/she can’t do anything about it because the geometry of the connector is fixed. By using a simulator, the designer can determine the impact on the signal integrity and can evaluate the effects on the system.