High Speed USB Platform Design Guidelines - Common Routing Mistakes

Stubs

A very common routing mistake is shown in Figure 4. Here the CAD designer could have avoided creating unnecessary stubs by proper placement of the pull down resistors over the path of the data traces. Once again, if a stub is unavoidable in the design, no stub should be greater than 200 mils.


Poor Routing Techniques

Picture below demonstrates several violations of good routing practices for proper impedance control and signal quality of high speed USB signaling.

Crossing a plane split

• The mistake shown here is where the data lines cross a plane split. This causes unpredictable return path currents and would likely cause a signal quality failure as well as creating EMI problems.

Creating a stub with a test point

• Here is another example where a stub is created that could have been avoided. Stubs typically cause degradation of signal quality and can also affect EMI.

Failure to maintain parallelism

• Picture below is also a classic example of a case where parallelism was not maintained, when it could have been. The red trace (the lighter trace farthest to the right with the “x” on it) shows the wrong way to route to the connector pins. The green trace (the darker trace in the middle) shows the correct way. Failing to maintain parallelism will cause impedance discontinuities that will directly affect signal quality. In this case it also contributes to the trace-length mismatch and will cause an increase in signal skew.

High Speed USB Platform Design Guidelines - Planes Guidelines

Plane Splits, Voids and Cut-Outs (Anti-Etch)

The following guidelines apply to the use of plane splits, voids and cutouts.

VCC Plane Splits, Voids, and Cut-Outs (Anti-Etch)

Use the following guidelines for the VCC plane.

1. Traces should not cross anti-etch, for it greatly increases the return path for those signal traces. This applies to High Speed USB signals, high-speed clocks and signal traces as well as slower signal traces, which might be coupling to them. USB signaling is not purely differential in all speeds (i.e. the FS Single Ended Zero is common mode)
2. Avoid routing of USB signals within 25 mils of any anti-etch to avoid coupling to the next split or radiating from the edge of the PCB.
3. When breaking signals out from packages it is sometimes very difficult to avoid crossing plane splits or changing signal layers, particularly in today’s motherboard environment that uses several different voltage planes. Changing signal layers is preferable to crossing plane splits if a choice has to be made between one or the other.
4. If crossing a plane split is completely unavoidable, proper placement of stitching caps can minimize the adverse effects on EMI and signal quality performance caused by crossing the split. Stitching capacitors are small-valued capacitors (1 mF or lower in value) that bridge voltage plane splits close to where high speed signals or clocks cross the plane split. The capacitor ends should tie to each plane separated by the split.


5. They are also used to bridge, or bypass, power and ground planes close to where a high-speed signal changes layers. As an example of bridging plane splits, a plane split that separates VCC5 and VCC3 planes should have a stitching cap placed near any high-speed signal crossing. One side of the cap should tie to VCC5 and the other side should tie to VCC3. Stitching caps provide a high frequency current return path across plane splits. They minimize the impedance discontinuity and current loop area that crossing a plane split creates.

GND Plane Splits, Voids, and Cut-Outs (Anti-Etch)

1. Use the following guideline for the GND plane.
2. Avoid anti-etch on the GND plane.

Layer Stacking

The following guidelines apply to PCB stack-up.

Four-layer Stack-Up

1. Signal 1 (top)
2. VCC
3. GND
4. Signal 2 (bottom, best layer for USB2)

The high speed USB validation motherboard used 7.5-mil traces with 7.5-mil spacing between differential pairs to obtain 90W differential impedance. The specific board stackup used is as follows:

• 1 ounce copper
• prepreg @ 4.5 mils
• core @ 53 mils
• board thickness @ 63 mils
• _r @ 4.5

Component Placement

The following guidelines apply to component placement on the PCB.

Locate high current devices near the source of power and away from any connector leaving the PCB (such as, I/O connectors, control and signal headers, or power connectors.) This reduces the length that the return current travels and the amount of coupling to traces that are leaving the PCB.

Keep clock synthesizers, clock buffers, crystals and oscillators away from the high speed USB host controller, high speed USB traces, I/O ports, PCB edges, front panel headers, power connector, plane splits and mounting holes. This reduces the amount of radiation that can couple to the USB traces and other areas of the PCB.

Position crystals and oscillators so that they lie flat against the PCB. Add a ground pad with the same or larger footprint under crystals and oscillators having multiple vias connecting to the ground plane. These will help reduce emissions.

High Speed USB Platform Design Guidelines - USB Trace

High Speed USB Trace Spacing

Use the following separation guidelines. Picture below provides an illustration of the recommended trace spacing.

1. Maintain parallelism between USB differential signals with the trace spacing needed to achieve 90 ohms differential impedance. Deviations will normally occur due to package breakout and routing to connector pins. Just ensure the amount and length of the deviations are kept to the minimum possible.
2. Use an impedance calculator to determine the trace width and spacing required for the specific board stackup being used. For the board stackup parameters, 7.5- mil traces with 7.5-mil spacing results in approximately 90 ohms differential trace impedance.
3. Minimize the length of high-speed clock and periodic signal traces that run parallel to high speed USB signal lines , to minimize crosstalk. Based on EMI testing experience, the minimum suggested spacing to clock signals is 50 mils.
4. Based on simulation data, use 20-mil minimum spacing between high-speed USB signal pairs and other signal traces for optimal signal quality. This helps to prevent crosstalk.

High Speed USB Termination

Use the following termination guidelines.

1. High-speed USB designs require parallel termination at both the transmitter and receiver. For host controller designs that use external termination resistors, place the termination resistors as close as possible to the host controller signal pins. Recommend less than 200 mils if possible. Follow the manufacturer’s recommendation for the termination value needed to obtain the required 45 ohm-toground parallel HS termination.
2. For downstream ports, a 15 kW pull down resistor on the connector side of the termination is required for device connection detection purposes. Note that this pull down might be integrated into the host controller silicon. Follow the manufacturer’s recommendation for the specific part used.
3. A common mode (CM) choke should be used to terminate the high speed USB bus if they are need to pass EMI testing. Place the CM choke as close as possible to the connector pins. See Section 5.1 for details.

Note: Common mode chokes degrade signal quality, thus they should only be used if EMI is a known problem.


High Speed USB Trace Length Matching

Use the following trace length matching guidelines.

1. High-speed USB signal pair traces should be trace-length matched. Max trace-length mismatch between
2. High-speed USB signal pairs (such as, DM1 and DP1) should be no greater than 150 mils.

High Speed USB Platform Design Guidelines - Layout Guidelines

General Routing and Placement

Use the following general routing and placement guidelines when laying out a new design. These guidelines will help to minimize signal quality and EMI problems. The high speed USB validation efforts focused on a four-layer motherboard where the first layer is a signal layer, the second layer is power, the third layer is ground and the fourth is a signal layer. This results in placing most of the routing on the fourth layer closest to the ground layer, and allowing a higher component density on the first layer.

1. Place the high-speed USB host controller and major components on the unrouted board first.
2. With minimum trace lengths, route high-speed clock and high-speed USB differential pairs first. Maintain maximum possible distance between high-speed clocks/periodic signals to high speed USB differential pairs and any connector leaving the PCB (such as, I/O connectors, control and signal headers, or power connectors).
3. Route high-speed USB signals on bottom whenever possible.
4. Route high-speed USB signals using a minimum of vias and corners. This reduces signal reflections and impedance changes.
5. When it becomes necessary to turn 90°, use two 45° turns or an arc instead of making a single 90° turn. This reduces reflections on the signal by minimizing impedance discontinuities.


6. Do not route USB traces under crystals, oscillators, clock synthesizers, magnetic devices or ICs that use and/or duplicate clocks.
7. Stubs on high speed USB signals should be avoided, as stubs will cause signal reflections and affect signal quality. If a stub is unavoidable in the design, no stub should be greater than 200 mils.
8. Route all traces over continuous planes (VCC or GND), with no interruptions. Avoid crossing over anti-etch if at all possible. Crossing over anti-etch (plane splits) increases inductance and radiation levels by forcing a greater loop area. Likewise, avoid changing layers with high-speed traces as much as practical. It is preferable to change layers to avoid crossing a plane split. Refer to Section 3.6 Plane Splits, Voids and Cut-Outs (Anti-Etch) for more details on plane splits.
9. Separate signal traces into similar categories and route similar signal traces together (such as routing differential pairs together).
10. Keep high-speed USB signals clear of the core logic set. High current transients are produced during internal state transitions and can be very difficult to filter out.
11. Follow the 20*h thumb rule by keeping traces at least 20*(height above the plane) away from the edge of the plane (VCC or GND, depending on the plane the trace is over). For the suggested stackup the height above the plane is 4.5 mils. This calculates to a 90-mil spacing requirement from the edge of the plane. This helps prevent the coupling of the signal onto adjacent wires and also helps prevent free radiation of the signal from the edge of the PCB.

Bypass Capacitor Connection to USB Port

Capacitors should be placed as close as possible to the port and the power-carrying traces should be as wide as possible, preferably, a plane. There should also be double vias on power and ground nets and the trace lengths should be kept as short as possible. Standard bypass routing and design methods should be used at all times to minimize inductance and resistance between bypass bulk storage capacitors and the USB connectors.


VBUS Trace Width

The trace width for the VBUS current path from the VBUS source to the bypass bulk storage capacitor, over current protection device, and USB connector power and ground pins should be at least 0.050-in.-wide, with 1.5-oz. to 2-oz. copper on outer layer, to ensure adequate current carrying capability.



It is essential to make the power-carrying traces wide enough that the system over current protection will trip instead of fusing the board traces in an overload event. Depending on the rating of the over current protection device, a good “rule of thumb” is to ensure the power-carrying traces are wide enough to carry at least twice the amperage rating of the over current protection device.

Most motherboards use a long route for VBUS, as seen in Figure 4, that must be sufficiently wide in order to support the number of USB ports on the back panel. The power-handling capacity of a printed circuit trace depends mostly on its cross sectional area and the allowable temperature rise.

USB 2.0 Board Design and Layout Guidelines

Clock frequencies generate the main source of energy in a USB design. The USB differential DP/DM pairs operate in high-speed mode at 480 Mbps. System clocks can operate at 12 MHz, 48 MHz, and 60 MHz. The USB cable can behave as a monopole antenna; take care to prevent RF currents from coupling onto the cable.

When designing a USB board, the signals of most interest are:

1. Device interface signals: Clocks and other signal/data lines that run between devices on the PCB.
2. Power going into and out of the cable: The USB connector socket pin 1 (VBUS ) may be heavily filtered and need only pass low frequency signals of less than ~100 KHz. The USB socket pin 4 (analog ground) must be able to return the current during data transmission, and must be filtered sparingly.
3. Differential twisted pair signals going out on cable, DP and DM: Depending upon the data transfer rate, these device terminals can have signals with fundamental frequencies of 240 MHz (high speed), 6 MHz (full speed), and 750 kHz (low speed).
4. External crystal circuit (device terminals XI and X0): 12 MHz, 19.2 MHz, 24 MHz, and 48 MHz fundamental. When using an external crystal as a reference clock, a 24 MHz and higher crystal is highly recommended.

General Routing and Placement

Use the following routing and placement guidelines when laying out a new design for the USB physical layer (PHY). These guidelines help minimize signal quality and electromagnetic interference (EMI) problems on a four-or-more layer evaluation module (EVM).

1. Place the USB PHY and major components on the un-routed board first.
2. Route the high-speed clock and high-speed USB differential signals with minimum trace lengths.
3. Route the high-speed USB signals on the plane closest to the ground plane, whenever possible.
4. Route the high-speed USB signals using a minimum of vias and corners. This reduces signal reflections and impedance changes.
5. When it becomes necessary to turn 90°, use two 45° turns or an arc instead of making a single 90° turn. This reduces reflections on the signal traces by minimizing impedance discontinuities.
6. Do not route USB traces under or near crystals, oscillators, clock signal generators, switching regulators, mounting holes, magnetic devices or IC’s that use or duplicate clock signals.
7. Avoid stubs on the high-speed USB signals because they cause signal reflections. If a stub is unavoidable, then the stub should be less than 200 mils.
8. Route all high-speed USB signal traces over continuous planes (VCC or GND), with no interruptions. Avoid crossing over anti-etch, commonly found with plane splits.

Board Stackup
Because of the high frequencies associated with the USB, a printed circuit board with at least four layers is recommended; two signal layers separated by a ground and power layer as shown below:


The majority of signal traces should run on a single layer, preferably SIGNAL1. Immediately next to this layer should be the GND plane, which is solid with no cuts. Avoid running signal traces across a split in the ground or power plane. When running across split planes is unavoidable, sufficient decoupling must be used. Minimizing the number of signal vias reduces EMI by reducing inductance at high frequencies.

Cable Connector Socket

Short the cable connector sockets directly to a small chassis ground plane (GND strap) that exists immediately underneath the connector sockets. This shorts EMI (and ESD) directly to the chassis ground before it gets onto the USB cable. This etch plane should be as large as possible, but all the conductors coming off connector pins 1 through 6 must have the board signal GND plane run under. If needed, scoop out the chassis GND strap etch to allow for the signal ground to extend under the connector pins. Note that the etches coming from pins 1 and 4 (VBUS power and GND) should be wide and via-ed to their respective planes as soon as possible, respecting the filtering that may be in place between the connector pin and the plane. See picture for a schematic example.

Place a ferrite in series with the cable shield pins near the USB connector socket to keep EMI from getting onto the cable shield. The ferrite bead between the cable shield and ground may be valued between 10 W and 50 W at 100 MHz; it should be resistive to approximately 1 GHz. To keep EMI from getting onto the cable bus power wire (a very large antenna) a ferrite may be placed in series with cable bus power, VBUS, near the USB connector pin 1. The ferrite bead between connector pin 1 and bus power may be valued between 47 W and approximately 1000 W at 100 MHz. It should continue being resistive out to approximately 1 GHz, as shown in below.

USB 2.0 Differential Trace DP/DM and Crystal Oscillator

USB 2.0 Differential Trace DP/DM

Place the USB PHY as close as possible to the USB 2.0 connector. The signal swing during high-speed operation on the DP/DM lines is relatively small (400 mV ± 10%), so any differential noise picked up on the twisted pair can affect the received signal. When the DP/DM traces do not have any shielding, the traces tend to behave like an antenna and picks up noise generated by the surrounding components in the environment. To minimize the effect of this behavior:

1. DP/DM traces should always be matched lengths and must be no more than 4 inches in length; otherwise, the eye opening may be degraded as shown below.
2. Route DP/DM traces close together for noise rejection on differential signals, parallel to each other and within two mils in length of each other (start the measurement at the chip package boundary, not to the balls or pins).
3. A high-speed USB connection is made through a shielded, twisted pair cable with a differential characteristic impedance of 90 W ±15%. In layout, the impedance of DP and DM should each be 45 W ± 10%.
4. DP/DM traces should not have any extra components to maintain signal integrity. For example, traces cannot be routed to two USB connectors.

DP/DM Vias

When a via must be used, increase the clearance size around it to minimize its capacitance. Each via introduces discontinuities in the signal’s transmission line and increases the chance of picking up interference from the other layers of the board. Be careful when designing test points on twisted pair lines; through-hole pins are not recommended.

Crystals / Oscillator

Keep the crystal and its load capacitors close to the USB PHY pins, XI and XO (see Figure 5). Note that frequencies from power sources or large capacitors can cause modulations within the clock and should not be placed near the crystal. In these instances, errors such as dropped packets occur. A placeholder for a resistor, in parallel with the crystal, can be incorporated in the design to assist oscillator startup.

Power is proportional to the current squared. The current is I = C*dv/dt, since dv/dt is a function of the PHY, current is proportional to the capacitive load. Cutting the load to decreases the current by and the power to 1/4 the original value.

Image Plance for USB 2.0

An image plane is a layer of copper (voltage plane or ground plane), physically adjacent to a signal routing plane. Use of image planes provides a low impedance, shortest possible return path for RF currents. For a USB board, the best image plane is the ground plane because it can be used for both analog and digital circuits.

1. Do not route traces so they cross from one plane to the other. This can cause a broken RF return path resulting in an EMI radiating loop as shown below. This is important for higher frequency or repetitive signals. Therefore, on a multi-layer board, it is best to run all clock signals on the signal plane above a solid ground plane.
2. Avoid crossing the image power or ground plane boundaries with high-speed clock signal traces immediately above or below the separated planes. This also holds true for the twisted pair signals (DP,DM). Any unused area of the top and bottom signal layers of the PCB can be filled with copper that is connected to the ground plane through vias.

Do not overlap planes that do not reference each other. For example, do not overlap a digital power plane with an analog power plane as this produces a capacitance between the overlapping areas that could pass RF emissions from one plane to the other, as shown in below.



Avoid image plane violations. Traces that route over a slot in an image plane results in a possible RF return loop, as shown in below.