General Routing Techniques with Emphasis on PI6C10X Clocks -- > Part 3

Clock traces can easily become antennas. 100 MHz clock running through a narrow trace can radiate EMI and affect the FM radio sitting next to the system. As is evident, 100MHz is right at the middle of the FM radio spectrum. The way to further decrease the EMI radiation is to guard against improper loading and mismatches. To practically eliminate this problem, the source impedance of the clock driver should be matched in impedance to the load and the circuit trace. Most often a series termination is placed as close as possible to the source.


Theoretically the output impedance of the clock driver plus the value of the termination should be equal to the impedance of the PCB transmission line. If there is an impedance mismatch between the low-impedance source and high-impedance load, voltage reflection can occur from the load. This will result in overshoot and undershoot of the signal. The output impedance of the clock driver ranges from 20 to 30 ohms. To match this with a 50-ohms transmission line, a 30 to 20 ohms damping resistor should be chosen. The draw back is that the termination resistor reduces the amount of current and in effect reduces the clock waveform rise and fall time.
It is very important to choose a proper value of damping resistor since any excessive voltage drop may increase the clock Jitter.

To reduce ground bounce that causes Jitter, a full ground plane under the device is necessary. All bypass capacitors are connected to this ground plane. Each ground pin should be connected to the ground plane individually. Daisy chain grounding should not be practiced since it allows sharing the ground path. No high frequency signal should be routed under the device since high frequency clocks tend to capacitive and inductively couple into the device and cause Jitter in the PLL. Picture shown below, illustrate the recommended PCB layout for the power supply bypassing the clock generator and the CK100 clock buffer, respectively. This method dramatically reduces the noise that may enter the PLL and cause Jitter. The value of the resistor should not be too high to stop the device from proper functioning.

The PI6C18X Clock Buffer

The PI6C18X is a buffer device that removes large switching current from the actual clock generation device. The PI6C18X, however, introduces a delay of up to 5ns. The Intel chipset and new chipsets resolve this problem by providing the clock to the PI6C18X. The chipset can read the exact amount of the delay and can compensate for this delay. In effect the chipset adjusts the SDRAM timing to optimize the relationship between CPU and SDRAM timing.

EMI Reducing Capacitors

If the amount of EMI is still very high in a system, it is possible to alleviate this condition even further by using a special type of capacitor. The EMI reducing capacitor is mainly used on the output clocks to round the falling and rising edges of the clock and hence reduce the radiation from sharp edges. The EMI reduction capacitors usually range from 4pF to 25pF. They are placed very close to terminating resistors between the resistor and the load. No connection should be made to clocks that are not used. No termination is recommended for unused clock pins. Since these devices are CMOS, they draw large impulse current. If the power supply bypassing is not adequate, the noise as the result of these transitions may enter the device analog section and increase the jitter. Where possible, disable unused clock outputs.

Ground Plane Localization

The entire board must have a separate ground plane, however, it is strongly recommended to localize the ground plane for the clock generator. This localized ground plane is then connected to the main board ground plane through Vias and device pins.

Other Routing Issues

The clock must be placed near the center of the board and near a chassis ground. Clock traces should not intersect each other. All clock signals must be hand routed before any other signals.

More tips on routing and connections: Do not use 90 degree angles when routing clock traces. If possible, always use curvy traces. Do not route any other signals below the clock generator. A solid ground plane must be placed on the layer adjacent to a clock trace routing layer. Vias should be avoided on clock signals. Vias cause reflection by changing trace impedance. Vias should not cause discontinuities either. For low skew, signal traces must be of matched length and loading, and, if possible, identical. If certain signals are supposed to have certain skews with each other, their trace length must be equal. Do not use T connections. For minimum
skew, use one load per clock output.



Board Layout for Reducing EMI and Preserving Signal Integrity

It is recommended that you calculate the capacitive loading and compensate with a series damping resistor and/or end termination. Do not locate clock signals near I/O areas. To minimize reflections and ringing keep trace impedance balanced and short. It is highly recommended that you rout clock traces on one routing plane only. At all times this layer must be adjacent to a solid image plane. It is better to create localized ground and VCC planes on the top layer of the PCB. The localized ground plane should be beneath the chip and the VCC plane surrounds the chip. These planes provide a path for RF currents to return to ground.