AC Coupling Capacitors for PCI Express

PCI Express requires AC coupling between transmitter and receiver. The AC coupling capacitors for both differential pair signals must be the same value, same package size, and have symmetric placement. If possible, TX traces should route on the top layer.

The capacitor value must be in the range of 75 nF to 200 nF (100 nF is best). The 0402 package size is preferred, and 0603 is acceptable. C-pack is not allowed.

The breakout into and out of capacitors should be symmetrical for both signal lines in a differential pair. The trace separation for routing to pads must be minimized in order to optimize tight coupling between the signal pairs.

Bypass or De-coupling Capacitors Considerations

Power supply de-coupling is now standard practice in digital design but we’ll mention it here because of its importance in removing supply line noise. High-frequency noise on power supplies causes problems for nearly every digital device. Such noise is typically generated by ground bounce, radiating signals or even by the digital device itself. The simplest method of curing power supply noise is to use de-couple the high-frequency noise to ground via capacitors. Ideally, the de-coupling capacitors provide a low-impedance path to ground for the high-frequency noise, hence ‘cleaning’ the power supply. The choice of de-coupling capacitors depends on the application. Most designs will locate surface mount chip capacitors as close to the power pins as physically possible. The value of these capacitors must be great enough to provide a low-impedance path for the anticipated power supply noise. A common problem with de-coupling capacitors is that they often don’t behave like capacitors. There are several reasons for this:

• The capacitor packaging includes some amount of lead inductance;
• Capacitors also have an amount of Equivalent Series Resistance (ESR);
• The trace between the power pin and the de-coupling capacitor has some amount of series inductance;
• The trace between the ground pin and the ground plane also has some amount of series inductance.

The cumulative effect of these problems is that:

• The capacitor will resonate at a particular frequency and the impedance of the network will greatly change as that frequency is neared;
• The ESR hampers the low-impedance path for the high-speed noise being de-coupled.

There are several things a digital designer can to counter these effects:

• The traces emanating from the VCC and GND pins on the device need to be as low-inductance as possible. This is done by making them as short and wide as the physical constraints allow;
• Choosing a capacitor with a lower ESR will improve the power supply de-coupling.
• Choosing a smaller package for the capacitor will reduce the package inductance. The trade-off for using a smaller package is the capacitance variation over temperature. After selecting a capacitor, these specs need to be verified for the design requirements;
• The last point can introduce a trap for the unwary. For example, using a Y5V capacitor instead of an X7R device may allow for a smaller package and hence lower inductance, but this is at the cost of poor performance at high temperature.
• A further point to consider is that a larger capacitor is often employed to provide bulk storage on the board as well as implementing low-frequency de-coupling. These capacitors are distributed more sparingly and are often electrolytic or tantalum devices.