Wednesday, June 24, 2009

General Routing Techniques with Emphasis on PI6C10X Clocks -- > Part 1

Advanced process technology provides market specifications for Skew, Jitter, and EMI. In addition, Pericom’s devices provide lower power consumption, smaller board space, lower operating temperature, and lower cost requirements.

To avoid poor quality clock transmission, it is very important to consider certain clock layout and routing techniques. This application note is concerned with power supply filtering, bypassing, and routing techniques for crystal, ground and power supply. Since these techniques concern power and ground, they apply to almost every clock. The application note discusses some of the existing terms and problems faced by design engineers when using clocks in their systems. It also discusses the techniques to eliminate or alleviate such problems.


The deviation in clock output transitions from their ideal positions is called Jitter, measured Cycle-to-Cycle. Jitter is the measure of the difference in the period of successive cycles of a continuous clock pulse see picture below. The aim of this application note is to show techniques that reduce Jitter and eliminate their causes.

Long Term Jitter is the difference in a clock output transition from its ideal position over many cycles (10 to 20 microseconds, see picture below. To reduce Jitter we need to understand that Power Supply Noise, Ground Bounce, PLL, Random Thermal Noise, and Random Mechanical Noise are its causes. Eliminating ground bounce and reducing power supply noise significantly reduces Jitter.

Period Jitter is the measure of maximum change in a clock’s output transition from its ideal position during a single period.

Reducing Power Supply Noise

Filtering method and bypassing are the most frequent ways of reducing the power supply noise. Placing a large tantalum capacitor connected to the source eliminates power supply ripple and current surges. For high frequency ripple elimination, small capacitor (0.1mF) on every Vdd of clock generator significantly reduces the high frequency ripples. To eliminate the noise coupling effect, no high frequency signals should be routed around or under the clock generator. We will discuss these techniques in more detail.

Eliminating Ground Bounce

Reducing the number of output loads can significantly eliminate ground bounce. Large and/or multilevel PCB Ground Planes also help to reduce ground bounce. Do not short individual ground pins together. Always connect each separately to a large ground plane. Large output currents also cause ground bounce. Limiting the output current can reduce ground bounce very effectively. If possible, always disable unused outputs.

Board Skew

Unequal trace lengths and loads cause the board skew independent of the skew generated by the buffer. To minimize board skew the design should have equal trace length and loads as much as possible.

Output Skew

This is the difference between two concurrent clock outputs that originate from a single input. Skew is mainly the variation in arrival time of two clock signals that are specified to occur at the same time. Skew is composed of the output skew of the driving device and the variation in the board delays caused by the layout variation of the output traces. Skew directly affects system margins by eroding the predictability of the arrival of a clock edge. Because elements in a synchronized system require clock signals to arrive at the same time, clock skew reduces the time when information can be passed from one device to the next. As system speeds increase, clock skew becomes a larger portion of the total cycle time. Clock Skew can be as much as 20% of cycle time. When cycle time approaches 15ns or less clock skew becomes increasingly important. For high-speed systems, skew can only consume 10 percent of cycle time. Skew as a result of clock driver is called intrinsic skew and skew as result of layout is called extrinsic skew.

Overshoot and Undershoot

Clock generators have low output impedance. When a device drives a load with large input impedance while its own output impedance is low, there will be a mismatch between the low impedance source and high impedance load. Most often when the traces are long such a condition is significantly worsened. These cause voltage reflections resulting in high voltage overshoot on the rising clock edge and voltage undershoot on the falling clock edge. Proper termination techniques will help eliminating these conditions. We will discuss termination schemes in more detail.

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