Thursday, May 14, 2009

Serial ATA: Designing for high-speed storage

Serial advanced technology attachment (SATA) is rapidly growing and poised to reign as the most popular hard-drive interface for PC, server and consumer electronics applications.
With disk-based storage becoming increasingly important in all areas of the electronics market, system designers need to be aware of the many challenges associated with working with SATA Gen 1 (1.5Gbps) and Gen 2 (3.0Gbps) protocols. Furthermore, system designers need to be familiar with the new SATA features that make it far more useful and powerful than simple replacement for parallel ATA. Taking advantage of these features and overcoming the design hurdles are keys to making successful products that use SATA.

Challenges, recommendations Increasingly sophisticated PCB layouts have become critical to ensuring proper operation of high-speed signals. At multigigabit speeds, SATA Gen 1 and Gen 2 create small changes to the copper etch layout that significantly affect the performance of the circuit.
SATA signals have rise times of about 100ps. They are coupled with the limited transmission speed of electrical signals that even small lengths of etch must be treated as a transmission line because a significant portion of the rising (or falling) voltage is on the etch. Failure to account for high frequency effects usually lead to PCB designs that fail intermittently.

Here is a list of layout rules that can ensure a working FR4 PCB SATA implementation. These rules can be grouped into two general categories: designing with differential signals and avoiding impedance mismatches.

Designing with differential signals

  • SATA is a high-speed differential signal. The SATA connection has a transmit and receive pair that are matched to within 5mils. It is important to match the etch lengths of the differential pair so as not to increase bit-error rate and reduce signaling differences. Also, common-mode noise will be generated, which leads to greater EMI radiation. Route side-by-side on an outer layer of the board (microstrip). If the pair must be routed on a different layer, the etches should be lengthmatched on both sides of the vias.
  • Route differential pairs loosely, separating the etches of the pair by six to 10 times the etch height above the reference plane.
  • To reduce EMI, do not separate pair etches by more than 150mils.
  • SATA differential pairs should have a differential impedance of 100Ω.
  • To reduce crosstalk, keep other signals on the same layer a minimum distance of 10-15 times the etch height above the reference plane away from the differential pair.
  • Do not use test points on multigigabit differential signals.

Avoiding impedance mismatches

  • Watch out for incorrect etch width or height above the reference plane. Etch width and height above the reference plane determines the impedance of the etch.
  • Maintain a solid reference plane. There should be no reference plane cuts, or keepout areas within 10 times the etch height on either side of a high-speed etch.
  • Changes in etch width or height usually caused by using etches that are too narrow to reliably manufacture can cause problems. Minimum etch width and height should be 4mils.
  • Use 10nF capacitors with a 0402 package size to minimize the change in etch width to capacitor-pad width.
  • If possible, route on a single layer. If you must change layers, then care must be made to ensure a proper return current path that follows the change in layers.
  • Watch out for connector impedance design that does not match line impedance. Multigigabit signals require connectors specifically designed with matching-controlled impedances.
  • If possible, use only surfacemount parts instead of through-hole parts. Keep pin stubs to a minimum length. Excess pin length should be cut off as part of the PCB manufacturing process.
  • Try to maintain 10 times the etch height above the reference plane separation between high-speed signal etches and other etches on the same layer or features (including board edges and mounting holes).
  • Do not add test points (small pads or vias) to high-speed etches.
  • Ensure that the PCB fabrication does not add “thieving” within 10 times the etch Serial ATA: Designing for high-speed storage height of high-speed etches.
  • Following these general guidelines will help ensure a successful design.


  1. Hi,
    i was looking for some good information on printed circuit board and search ended on this blog.Thanx for providing such a nice information.


  2. Should add point on need to provide voids in ground planes directly below device pads to minimize impedance mismatching.