Saturday, July 11, 2009

Gigabit Ethernet Controller Design Guidelines --> Power and Ground Planes Considerations

The RJ-45 chassis ground and the digital ground should be isolated through a 1M Ohm resistor and a 0.1uF decoupling capacitor. And the gap between the chassis ground and digital ground must be wider than 60 mils.

All the digital and analog power planes for different voltage supplies should be isolated.

  1. The above figures are the Digital Power (VDDxx) and Analog Power (AVDDxx) planes diagram of an illustrative LAN board design. For exact layout pattern, ASIX Electronics provides some demo boards and the layout PCB files and Gerber files for customer reference.
  2. VDDK: Digital Core Power 2.5V
  3. VDD2: Digital I/O Power 2.5V
  4. AVDDK: Analog Core Power 2.5V

Provide a power plane right underneath the ASIX Ethernet controller such that the VCC pins can be contacted to the power plane without going through thin traces.

All power pins should be implemented with a decoupling capacitor, and the decoupling capacitor should be as close to the respective power pin of ASIX Ethernet controller as possible.

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