Assembly and PCB Layout Guidelines for Chip-Scale Packages

Introduction

The Chip-Scale Package (CSP) is a dual- or multi-layer plastic encapsulated BT-Epoxy type substrate with copper signal and plain layers. The small form factor allows for enhanced conduction of heat to the PCB and provides a stable ground through down bonds; as well as an electrical connection through conductive, die-attached material. The design of these dual- and multi-layer small body packages allows for flexibility and enhances electrical performance to high-speed operating frequency.

CSPs in multiple configurations: substrate ball pitch range from 0.4 mm to 0.8 mm, with a package body size of 4 x 4 mm to 14 x 14 mm, and overall package height of 0.73 mm to 1.35 mm. The package footprint and outlines are specified in JEDEC MO-195, JEDEC MO-205, and JEDEC Design Guide 4.5 "Fine-Pitch, Square Ball Grid Array Package (FBGA)".

This application note provides general guidelines for proper board design and surface mount process.



CSP Package Overview
Below illustrate how the package height is reduced to the minimum by having the die background resulting in a thinner substrate and lower-bond wire loops. Figure 3 on page 2 illustrates the detailed construction of the layer stack-up. CSPs have excellent thermal dissipation because the thinner die, due to backgrinding, enables a thinner substrate and smaller overall body. The efficient and compact design of CSPs reduces electrical parasitics.




Surface Mount Considerations for CSPs
Special considerations are needed to properly design the motherboard and to mount the package for enhanced thermal-, electrical-, and board-level performance. The amount of the standoff clearance required depends on the application. The PCB footprint design should take into account dimensional tolerance due to package, PCB, and board assembly.

A number of factors may have a significant effect on how CSPs are mounted on the board and the quality of the solder joints. Some of these are the amount of solder paste coverage, stencil type, type of via, board thickness, ball finish on the package, surface finish on the board, type of solder pasted, and reflow profile.

PCB Land Pad Design Guidelines
This section provides both package- and board-level routing constraints in describing the philosophy behind the recommended land pad patterns.

Solder Masking Considerations
Non-solder mask defined (NSMD) pads are recommended for CSPs because a copper etching process has tighter control than a solder masking process and improves the reliability of solder joints.

Pad Design Recommendations
The solder pad on the PCB should not be larger than the solder mask opening for the ball pad on the package. For optimal solder joint strength, Actel recommends a 1:1 ratio for the two pads as shown below.

Trace and Via Design Recommendations

The dog-bone style land pad layout is recommended for 0.8 mm to 0.5 mm land pitch with a through hole or micro via structure; for the 0.4 mm land pitch use the via in pad. The via in pad should be micro via, and the through holes will need tenting, as shown below.



Board Mounting Guidelines
This section provides guidelines for stencil design. Due to the small land surface area on the PCB surface, care must be taken to form reliable solder joints for the CSP. Actel recommends using stainless steel stencils with a thickness of 0.10 to 0.20 mm and metal squeegees. If polymer squeegees are used, the minimum durometer should be 90.

Stencil Design and Thickness
Stencils should be laser cut and electropolished. The polishing helps in smoothing the stencil walls, which results in better paste release. Positive taper with a bottom opening of 25 to 50 microns larger than the top can provide better solder paste release. The stencil aperture tolerance should be tightly controlled because tolerance can effectively reduce the aperture size.
To maintain proper stencil design, do not ever exceed an area ratio of 0.66 or aspect ratio of 1.5.

Solder Paste
Since not enough space is available underneath the part after reflow, use "no clean," type 3 or type 4 paste for mounting CSPs. Nitrogen purge is also recommended during reflow, as gases entrapped in the solder joint are the main cause of voiding. There should be sufficient dwell time in the molten state to ensure gases from the solder paste have time to separate and escape from the molten solder.