PCB Layout Recommendations for BGA Packages

Introduction

As Ball Grid Array (BGA) packages become increasingly more popular, it is important to understand how they are affected by various board layout techniques. This document provides a brief overview of PCB layout considerations when working with BGA packages. It outlines some of the most common problems and provides tips for avoiding them at the design stage.

BGA Advantages
One of the greatest advantages of BGA packaging over other new technologies is that it can be supported with existing placement and assembly equipment. Most other new package types require new or upgraded processes, handlers and design methodologies. Incorporation of BGAs requires little more than a crash course in layout methodologies.

BGAs also offer significantly more misalignment tolerance, less susceptibility to coplanarity issues and easier PCB signal routing under a BGA package picture below.



BGA Disadvantages
The primary drawback of BGA packaging is the inability to access the solder joints for testing and inspection (a later section in this document provides layout recommendations for testing). At best, only the outermost row of balls can be seen, and board size and other components often restrict even that view. The best option available for a complete inspection of the device is an X-ray. By this means, the user can visually assess shorted connections, missing balls, filled vias, and in some cases opens see picture below. Opens and partial opens (where the solder did not wet the entire pad) are more difficult to see and may require higher resolution equipment.


PCB Layout
Both types of pad layout, Solder Mask Defined and Non- Solder Mask Defined (SMD and NSMD respectively), have been successfully applied to BGA applications. Each layout type offers some advantages over the other and either may recommended, depending on the source.

Solder Mask Defined Pads
In SMD pads, the solder mask comes up over the edge of the copper trace see picture below. This adds an element of strength to the pad for two reasons. First, the solder mask overlap provides extra strength to the adhesion bond between the copper and the glass/epoxy laminate. Second, because the copper needs to extend beyond the edge of the solder mask, the actual copper area is larger. This provides additional copper surface to which the laminate can adhere. This added strength may be important in cases where the pad-to-PCB attachment could fail due to board flexing or excessive temperature testing. Unfortunately, the larger copper area can also be a
drawback since it leaves less space between pads for routing signal traces. While this is generally not a serious problem, it is more likely to occur when signals are assigned to pins that lay near the center of a large matrix BGA. Therefore, it is suggested to keep as many pin assignments as possible towards the periphery of the device.


Non-Solder Mask Defined Pads
In an NSMD pad the solder mask does not overlap the edge of the copper; thus the size of the copper defines the size of the pad. While this technique lacks some of the adhesion strength of the SMD pad, it can produce a more uniform hot air solder leveled surface finish and can leave more room between pads for signal routing. The majority of BGA packages and designs use SMD type pads for added strength, however NSMD pads are gaining in popularity. Generally the best stress results come when the size of the PCB pad matches the size of the package pad. Be sure to check the specific pad information for the package being used.

Plated Through Hole Placement
Probably the most critical aspect of BGA PCB layout is the consideration for Plated Through Hole (PTH) placement. If the pad is too close or on top of the hole, or if there is no solder mask covering the via, then it is possible for the ball solder and paste to melt and be wicked into the
hole. If enough solder is lost into the hole, the result could be an open for that lead. While this type of defect can usually be detected in an X-ray, it is best avoided at layout see the second picture.

Pad Geometries
Pad geometries as shown in fourth and fifth picture) are typically circular. However, with a standard round pad, the X-ray of a soldered package looks the same regardless of the quality of wetting achieved; all that shows is the outline of the ball. By adding a slight variation in the shape of a dimple as shown in the last picture, it is possible to get a better X-ray view to check for opens. When the dimple feature is used, the solder wets to the entire pad surface and the ball deforms to the shape of the pad. This deformity is visible in an X-ray. The viewer must, however, learn to differentiate between a fully wet pad and one that simply has solder paste residue.





Layout Recommendations for Testability
Since it is impossible to probe BGA pins directly, PLD design and layout techniques that bring out several strategic pins as test points will allow testability of all of the internal PLD logic implementation. This simple solution can be combined with the ispANALYZER ™ software utility to provide full accessibility and testability to the PLD in a BGA package. The spANALYZER lets the user bring out internal macrocells (or other macrocell outputs) to unused I/O pins. With this capability, a suspect I/O pin can be tested via a test point that is designed to bring out a number of predefined I/O pins.

PCB design considerations when changing from 6-pin SOT23 to 6-pin WSON

What's the same?

1. The pin connectivity has not changed between similar products.
2. The overall space required on a PCB has not changed.
3. The pitch between pins has not changed.






What needs to be changed?

The 6-pin WSON package has an exposed pad (maximum size of 2.35mm x 1.45mm) on the underside of the package. There is no exposed pad on the 6-pin SOT23 package.

The underside (and hence the exposed pad) of the 6-pin WSON will be closer to the PCB surface, which needs to be taken into consideration for the PCB layout and solder stencil design. The exposed pad must be either isolated or grounded (connect to VSS).

If the 6-pin WSON package is used on an existing 6-pin SOT23 footprint, the exposed pad can create a short circuit between two or more pads.

Picture below shows an example 6-pin SOT23 (in blue) and 6-pin WSON (in red) PCB footprints 'superimposed'. The dotted line represents the exposed bottom pad on the 6-pin WSON. The noted dimensions of 1.20mm and 1.90mm show example separation of the PCB pads for 6-pin SOT23 and 6-pin WSON respectively.


If an existing PCB that uses the 6-pin SOT23 package is to be used for the 6-pin WSON package, there must be no bare traces under the exposed pad. The PCB pads could remain the same size, but the solder mask under the component must be increased in size accordingly to prevent short circuits between two or more of the pads. The solder stencil aperture size must then be modified to match the change in pad size.

Due to the design of the 6-pin WSON package (as with similar bottomonly solder contact parts), the PCB pads should ideally be narrower than those of 6-pin SOT23 parts. Although not necessary, the PCB pads for the 6-pin WSON can be extended beyond the component body
to allow for component misplacement and to also assist in manual soldering or rework. In the example shown in Picture below, the pads extend beyond the 6-pin WSON body by 0.45mm.


Picture below shows a suggested compromise pad layout, modified from an existing SOT-23 design. The copper pads are not changed, but the solder mask is made to cover the entire center area as well as part of the pads to a width of 1.90mm; the solder paste stencil is modified to
prevent solder paste from being deposited on top of solder mask. While the layout of above picture is preferred, the below picture layout can be an acceptable compromise if it is not possible to make changes to the copper layer.


One potential problem with the above picture method is that moisture due to humidity can get trapped between the exposed center pad and the underlying copper pads, causing erratic sensing behavior. Also, the solder mask can potentially have pinholes in it which could cause short circuits to the center pad. It is therefore much better to reduce the pad lengths as shown in above picture, if at all possible.

IPC-7351, 'The Generic Requirement for Surface Mount Design and Land Pattern Standard' should be referred to during the design stage, as well as considering other design influences, such as the required PCB finish. The design should be verified prior to high volume manufacturing.
The solder reflow profile should not require changing when moving from 6-pin SOT23 to 6-pin WSON packages (JEDEC J-STD-020).

Assembly and PCB Layout Guidelines for Chip-Scale Packages

Introduction

The Chip-Scale Package (CSP) is a dual- or multi-layer plastic encapsulated BT-Epoxy type substrate with copper signal and plain layers. The small form factor allows for enhanced conduction of heat to the PCB and provides a stable ground through down bonds; as well as an electrical connection through conductive, die-attached material. The design of these dual- and multi-layer small body packages allows for flexibility and enhances electrical performance to high-speed operating frequency.

CSPs in multiple configurations: substrate ball pitch range from 0.4 mm to 0.8 mm, with a package body size of 4 x 4 mm to 14 x 14 mm, and overall package height of 0.73 mm to 1.35 mm. The package footprint and outlines are specified in JEDEC MO-195, JEDEC MO-205, and JEDEC Design Guide 4.5 "Fine-Pitch, Square Ball Grid Array Package (FBGA)".

This application note provides general guidelines for proper board design and surface mount process.



CSP Package Overview
Below illustrate how the package height is reduced to the minimum by having the die background resulting in a thinner substrate and lower-bond wire loops. Figure 3 on page 2 illustrates the detailed construction of the layer stack-up. CSPs have excellent thermal dissipation because the thinner die, due to backgrinding, enables a thinner substrate and smaller overall body. The efficient and compact design of CSPs reduces electrical parasitics.




Surface Mount Considerations for CSPs
Special considerations are needed to properly design the motherboard and to mount the package for enhanced thermal-, electrical-, and board-level performance. The amount of the standoff clearance required depends on the application. The PCB footprint design should take into account dimensional tolerance due to package, PCB, and board assembly.

A number of factors may have a significant effect on how CSPs are mounted on the board and the quality of the solder joints. Some of these are the amount of solder paste coverage, stencil type, type of via, board thickness, ball finish on the package, surface finish on the board, type of solder pasted, and reflow profile.

PCB Land Pad Design Guidelines
This section provides both package- and board-level routing constraints in describing the philosophy behind the recommended land pad patterns.

Solder Masking Considerations
Non-solder mask defined (NSMD) pads are recommended for CSPs because a copper etching process has tighter control than a solder masking process and improves the reliability of solder joints.

Pad Design Recommendations
The solder pad on the PCB should not be larger than the solder mask opening for the ball pad on the package. For optimal solder joint strength, Actel recommends a 1:1 ratio for the two pads as shown below.

Trace and Via Design Recommendations

The dog-bone style land pad layout is recommended for 0.8 mm to 0.5 mm land pitch with a through hole or micro via structure; for the 0.4 mm land pitch use the via in pad. The via in pad should be micro via, and the through holes will need tenting, as shown below.



Board Mounting Guidelines
This section provides guidelines for stencil design. Due to the small land surface area on the PCB surface, care must be taken to form reliable solder joints for the CSP. Actel recommends using stainless steel stencils with a thickness of 0.10 to 0.20 mm and metal squeegees. If polymer squeegees are used, the minimum durometer should be 90.

Stencil Design and Thickness
Stencils should be laser cut and electropolished. The polishing helps in smoothing the stencil walls, which results in better paste release. Positive taper with a bottom opening of 25 to 50 microns larger than the top can provide better solder paste release. The stencil aperture tolerance should be tightly controlled because tolerance can effectively reduce the aperture size.
To maintain proper stencil design, do not ever exceed an area ratio of 0.66 or aspect ratio of 1.5.

Solder Paste
Since not enough space is available underneath the part after reflow, use "no clean," type 3 or type 4 paste for mounting CSPs. Nitrogen purge is also recommended during reflow, as gases entrapped in the solder joint are the main cause of voiding. There should be sufficient dwell time in the molten state to ensure gases from the solder paste have time to separate and escape from the molten solder.

POWER SUPPLY LAYOUT for RF Consideration

The most important requirement for the RF receiver modules to perform a wide range is a very stable and low noise supply voltage output. As important as the choice of power supply type and components is the design of the PCB to which these items are attached with regard to control both radiated and conducted emissions. The following recommendations apply also for designing the layout for additional electronics like digital circuits.

Since parasitic impedances increase with frequency, a simple PCB signal trace might become a complex path (antenna!), rather than just a low resistance with respect to DC measurements. Due to these parasitic impedances – both capacitive and inductive in nature, the layout of the PCB is very critical for the entire system.

Notes for Components Placement
1. Keep ground return paths short and wide. Provide a return path that creates the smallest loop for the current to return.

2. When routing the circuitry the analog small signal ground and the digital and power ground for switching currents must be kept separate.



3. It is suggested to isolate the analog circuitry on a local ground island, which can then be connected to the rest of the system ground at one single point. This helps to keep the analog ground clean and quiet. All connections between the analogue and digital circuitry should cross nearby single point.

Some general board layout guidelines
1. Use a multilayer PCB with separate GND and VCC planes. Keep connections between each supply pin and the corresponding power/ground plane as short as possible.

2. Try to make signal ground connections through Vias to the ground plane rather than through PCB traces. Any PCB trace acts as a transmit antenna.

3. Try to keep power ground, digital ground and analog ground separately. Tie the different grounds together (if they are electrically connected) at one single point near DC output return. Star grounding should be used whenever possible, as opposed to daisy chain grounding.

4. Minimize areas and lengths of loops which conduct high frequency switching currents see picture below. Magnetic coupling is a strong function of the loop area and is difficult to counteract, because a magnetic shield is usually required instead of simple copper shielding. Since PCBs use copper conductors, the traces and ground planes may be ineffective as shields against magnetic coupling.



5. Loop areas can be reduced by shortening the trace lengths and by routing signal traces next to their return paths, parallel to each other on adjacent layers. Loop areas can also be reduced by placing bypass capacitors as close to the noise source as possible.

6. Applicable to oscillators: if possible use a frequency (& harmonics) that falls outside the receiver working frequencies. Provide a guard ring tied to correspondingly ground for oscillator. Avoid routing below oscillator, area around and between oscillator and tracks filled with copper, Vias to appropiate ground.

7. DC/DC-converters particularly carry high frequency switching currents. For more information, please check individual manufacturer datasheets when using such components.

8. Place the filter capacitors so that their terminals are directly connected to the PCB traces that carry main current to be filtered (no extra trace length).

9. Keep the distance between the converter and the filter capacitors as short as possible to reduce parasitic effects and transient current flow.

10. Pick the smallest package for a given capacitance. Physically small capacitors tend to have lower parasitic inductance than physically large ones.

11. Also, a short capacitor has less inductance than a long capacitor, and a high profile capacitor has less inductance than a low profile capacitor. Use at least two capacitors which differ by a factor 100 in value to decouple. The reactance of large capacitors has a significant inductive component at higher frequencies.

12. Because of its inherent inductive component, a single large capacitor is not very effective against high frequency noise. Using paralleled capacitors like Tantalum (e.g. 22μF) in combination with ceramic capacitors (e.g. 0.1μF) reduces filter impedance across a wide frequency band see picture below. Among the paralleled capacitors: Place the ceramic capacitors closest to the device pin.

13. When laying out the PCB, always make provisions for as many noise suppression capacitors as possible. Consider this as risk reduction for the debug phase of your design. If the capacitors are not needed, just leave them out when the board is assembled.

14. For heavy environments you may also consider the use of shield planes and discrete inductors like ferrite beads or common mode chokes inserted into the signal or power line paths. Their handling requires however some experience.

15. If possible use a Spectral analyzer and a near field probe set to identify the interferences and their sources on PCB.