Tuesday, May 5, 2009

High Speed USB Platform Design Guidelines - Planes Guidelines

Plane Splits, Voids and Cut-Outs (Anti-Etch)

The following guidelines apply to the use of plane splits, voids and cutouts.

VCC Plane Splits, Voids, and Cut-Outs (Anti-Etch)

Use the following guidelines for the VCC plane.
  1. Traces should not cross anti-etch, for it greatly increases the return path for those signal traces. This applies to High Speed USB signals, high-speed clocks and signal traces as well as slower signal traces, which might be coupling to them. USB signaling is not purely differential in all speeds (i.e. the FS Single Ended Zero is common mode)
  2. Avoid routing of USB signals within 25 mils of any anti-etch to avoid coupling to the next split or radiating from the edge of the PCB.
  3. When breaking signals out from packages it is sometimes very difficult to avoid crossing plane splits or changing signal layers, particularly in today’s motherboard environment that uses several different voltage planes. Changing signal layers is preferable to crossing plane splits if a choice has to be made between one or the other.
  4. If crossing a plane split is completely unavoidable, proper placement of stitching caps can minimize the adverse effects on EMI and signal quality performance caused by crossing the split. Stitching capacitors are small-valued capacitors (1 mF or lower in value) that bridge voltage plane splits close to where high speed signals or clocks cross the plane split. The capacitor ends should tie to each plane separated by the split.

  5. They are also used to bridge, or bypass, power and ground planes close to where a high-speed signal changes layers. As an example of bridging plane splits, a plane split that separates VCC5 and VCC3 planes should have a stitching cap placed near any high-speed signal crossing. One side of the cap should tie to VCC5 and the other side should tie to VCC3. Stitching caps provide a high frequency current return path across plane splits. They minimize the impedance discontinuity and current loop area that crossing a plane split creates.

GND Plane Splits, Voids, and Cut-Outs (Anti-Etch)

  1. Use the following guideline for the GND plane.
  2. Avoid anti-etch on the GND plane.

Layer Stacking

The following guidelines apply to PCB stack-up.

Four-layer Stack-Up
  1. Signal 1 (top)
  2. VCC
  3. GND
  4. Signal 2 (bottom, best layer for USB2)

The high speed USB validation motherboard used 7.5-mil traces with 7.5-mil spacing between differential pairs to obtain 90W differential impedance. The specific board stackup used is as follows:

  • 1 ounce copper
  • prepreg @ 4.5 mils
  • core @ 53 mils
  • board thickness @ 63 mils
  • _r @ 4.5

Component Placement

The following guidelines apply to component placement on the PCB.

Locate high current devices near the source of power and away from any connector leaving the PCB (such as, I/O connectors, control and signal headers, or power connectors.) This reduces the length that the return current travels and the amount of coupling to traces that are leaving the PCB.

Keep clock synthesizers, clock buffers, crystals and oscillators away from the high speed USB host controller, high speed USB traces, I/O ports, PCB edges, front panel headers, power connector, plane splits and mounting holes. This reduces the amount of radiation that can couple to the USB traces and other areas of the PCB.

Position crystals and oscillators so that they lie flat against the PCB. Add a ground pad with the same or larger footprint under crystals and oscillators having multiple vias connecting to the ground plane. These will help reduce emissions.

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