Circuit Board Decoupling Guidelines

Power Bus Decoupling Guidelines for Printed Circuit Boards without Power Planes

Applicable to:

1- or 2-sided boards or multi-layer boards that do not employ planes for power distribution

General Guidelines

• Provide at least one "local" decoupling capacitor for each active device and at least one larger "bulk" decoupling capacitor for each voltage distributed on the board.

• Local decoupling capacitors should be connected between the voltage and ground pins of the active device. the area of the loop formed by the capacitor/device connection should be minimized.

• Local decoupling capacitors typically have nominal values of 0.001, 0.01 or 0.047 microfarads. Some active devices may require several local decoupling capacitors in order to respond to a sudden demand for current.
  

• Bulk decoupling capacitors should be located near the point where a voltage comes on to the board. If the voltage is generated on the board, the bulk decoupling should be near the location where it is generated.

• Bulk decoupling capacitors should be sized to meet the transient current needs of the entire board. Typically, bulk decoupling capacitors have values equal to 1 - 10 times the sum of the values of the local decoupling capacitors connected to the same bus.

• As a general rule, two local decoupling capacitors with the same nominal value are better than one capacitor with twice the nominal value. Two capacitors have a lower overall connection inductance and provide better high-frequency filtering to the rest of the power bus.

See Example Below for good local decoupling capacitor connections to boards without power planes.

Power Bus Decoupling Guidelines for Printed Circuit Boards with Closely Spaced Power Distribution Planes

Applicable to:

Multi-layer boards with power distribution planes spaced ~0.3 mm or less apart

General Guidelines

• Multi-layer boards generally employ two types of decoupling capacitor. Large-valued "bulk" capacitors help to minimize the impedance of the power bus at low frequencies (e.g. below a few hundred kHz). Smaller "local" capacitors reduce the power bus impedance at higher frequencies (e.g. up to ~ 100 MHz on boards with closely spaced planes). At even higher frequencies, the power bus impedance is determined by the planes themselves.

• Boards typically have one or two large electrolytic bulk decoupling capacitors or they may employ half a dozen or more bulk decoupling capacitors in smaller packages. Either approach is effective and this decision is normally made based on size, cost and board-area constraints.

• The total value of the bulk decoupling is determined by the transient power requirements of the active devices on the board (See: "How much decoupling capacitance do I need?") Generally, the total bulk decoupling capacitance is 1 - 10 times the total local decoupling capacitance connected to the power bus.

• Local decoupling capacitors are intended to be effective at higher frequencies. The inductance of their connection to the power distribution planes is far more critical than their nominal capacitance. Generally, smaller package sizes can be connected to the planes with a lower inductance than larger packages. Therefore, local decoupling capacitors should be as small as possible.

• Choose the largest nominal capacitance available in a given package size. However, do not use capacitors that have a nominal capacitance less than the parallel plate capacitance that naturally occurs between the power and power-return planes [C=eA/d]. A board made with FR-4 material containing one pair of power distribution planes spaced 0.25 mm (10 mils) apart has an interplane capacitance of approximately 16 pF/cm2.

• The location of the local decoupling capacitors is not critical because their performance is dominated by the inductance of their connection to the planes. At the frequencies where they are effective they can be located anywhere within the general vicinity of the active devices [1].

• The maximum frequency at which the capacitors will be effective is proportional to the square root of the number of capacitors [1]. Therefore, high-speed circuit boards often have many local decoupling capacitors for every active device on the board.

• Connection inductance is determined by the loop area formed by the capacitor body, mounting pads, traces and vias.
  

  To minimize connection inductance:

  • Never use traces! Locate the via adjacent to the mounting pad.

  • If there is no room for the via adjacent to the pad, then move the whole capacitor. Capacitor location doesn't matter, but connection inductance is critical.

  • Locate the two vias as close together as possible.

  • Four vias (instead of two) will cut the connection inductance nearly in half.

  • Mount all of the local decoupling capacitors on the face of the board nearest to the planes. Connection inductance is nearly proportional to the distance from the planes.

See example below for local decoupling capacitor connections to boards with closely spaced power distribution planes. Connections with lower inductance will be more effective at higher frequencies.

Power Bus Decoupling Guidelines for Printed Circuit Boards with Widely Spaced Power Distribution Planes

Applicable to:

Multi-layer boards with power distribution planes spaced more than 0.5 mm apart

Introduction

• In boards with widely-spaced power distribution planes, the inductance due to the loop area between the planes cannot be neglected. In fact, this inductance can be used to enhance the board's power bus decoupling.

• Local decoupling capacitors on boards with widely spaced planes can effectively reduce noise on the power bus at frequencies up to several GHz if they are mounted properly.

• The mutual inductance between closely spaced vias can force current to be drawn from a nearby decoupling capacitor before it is drawn from the power distribution planes [1-3].

• In order to take advantage of this phenomenon, it is important that the connection inductance of the local decoupling capacitors is minimized. It is also important to locate these capacitors very near to the device being decoupled.

General Guidelines

• Multi-layer boards generally employ two types of decoupling capacitor. Large-valued "bulk" capacitors help to minimize the impedance of the power bus at low frequencies (e.g. below a few hundred kHz). Smaller "local" capacitors reduce the power bus impedance at higher frequencies.

• Boards typically have one or two large electrolytic bulk decoupling capacitors or they may employ half a dozen or more bulk decoupling capacitors in smaller packages. Either approach is effective and this decision is normally made based on size, cost and board-area constraints.

• The total value of the bulk decoupling is determined by the transient power requirements of the active devices on the board (See: "How much decoupling capacitance do I need?") Generally, the total bulk decoupling capacitance is 1 - 10 times the total local decoupling capacitance connected to the power bus.

• Local decoupling capacitors are intended to be effective at higher frequencies. The inductance of their connection to the power distribution planes is far more critical than their nominal capacitance. Generally, smaller package sizes can be connected to the planes with a lower inductance than larger packages. Therefore, local decoupling capacitors should be as small as possible.

• Choose the largest nominal capacitance available in a given package size. Nominal capacitance values are not nearly as critical as connection inductance. Typically, local decoupling capacitors on boards with widely spaced planes have a nominal value of about 0.01 microfarads.

• The location of the local decoupling capacitors is critical. Local decoupling capacitors should be located as close as possible to the power or ground pins of the active device they are decoupling. To determine near which pin to locate the decoupling capacitor (e.g. Vcc, Vss, Vdd, GND), first determine which power distribution plane is furthest from the active device. Local decoupling should be provided near the pins that connect to the most distant plane. For example, if the components are above Layer 1 on a 4-layer board and Layers 2 and 3 are Vcc and GND respectively, then the decoupling capacitors should be located near the GND pins of the active device. If there are any active devices below Layer 4 on this board, then decoupling for these devices should be located next to the Vcc pins.

• Orient the local decoupling capacitor so that the pin connected to the most distant plane is nearest the active device's pin connecting to the most distant plane. For example, in the board above if the active device is above Layer 1, and the decoupling capacitor is below Layer 4, then the Vcc pin of the decoupling capacitor should be located near the GND pin of the active device. Decoupling capacitors should never share a via with an active device when they are located on opposite sides of the board.

• If the decoupling capacitor can be located near enough to the active device to share the same via, this is optimal. However under no circumstances should a trace be used between the decoupling capacitor mounting pads and the vias. Decoupling capacitors should have vias located in or adjacent to the mounting pads to minimize their connection inductance. To minimize connection inductance:

  • Never use traces on decoupling capacitors! Locate the via adjacent to the mounting pad.

  • Locate the two capacitor vias as close together as possible.

  • Mount all of the local decoupling capacitors on the face of the board nearest to the planes. Connection inductance is nearly proportional to the distance from the planes.

See example below for good local decoupling capacitor connections to boards with widely spaced power distribution planes.