The first layout in above picture places the clocks and data converters adjacent to noisy components. Noise will be coupled into the sensitive circuits and their performance will be compromised. The second layout is much better as the sensitive circuits are physically isolated from the power supply, high-speed logic and digital I/O.
This blog presents the most common design issues affecting signal integrity in high-speed digital hardware design. These include impedance control, terminations, ground/power planes, signal routing and crosstalk. Armed with the knowledge presented here, a digital designer will be able to recognize potential signal integrity problems at the earliest design stage. Also, they will be able to apply techniques presented to prevent these issues affecting the performance of their design.
Sunday, August 31, 2008
Component Placement
Components on a PCB operate a variety of edge rates and have varying levels of tolerance to noise. The most straightforward method for improving SI is to physically isolate components on the PCB according to their edge rates and sensitivity. An example is shown below. In this example, the power supply, digital I/O and high-speed logic are considered to be high-threat circuits to the sensitive clock and data converter circuits.
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The first layout in above picture places the clocks and data converters adjacent to noisy components. Noise will be coupled into the sensitive circuits and their performance will be compromised. The second layout is much better as the sensitive circuits are physically isolated from the power supply, high-speed logic and digital I/O.
The first layout in above picture places the clocks and data converters adjacent to noisy components. Noise will be coupled into the sensitive circuits and their performance will be compromised. The second layout is much better as the sensitive circuits are physically isolated from the power supply, high-speed logic and digital I/O.
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